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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AT83SND2CMP3B датащи(PDF) 38 Page - ATMEL Corporation |
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AT83SND2CMP3B датащи(HTML) 38 Page - ATMEL Corporation |
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38 / 241 page  38 4341F–MP3–03/06 AT8xC51SND2C/MP3B Table 9-2. Priority Levels A low-priority interrupt is always interrupted by a higher priority interrupt but not by another inter- rupt of lower or equal priority. Higher priority interrupts are serviced before lower priority interrupts. The response to simultaneous occurrence of equal priority interrupts is determined by an internal hardware polling sequence detailed in Table 9-3. Thus, within each priority level there is a second priority structure determined by the polling sequence. The interrupt control system is shown in Figure 9-1. Table 9-3. Priority within Same Level IPHxx IPLxx Priority Level 0 0 0 Lowest 01 1 10 2 1 1 3 Highest Interrupt Name Priority Number Interrupt Address Vectors Interrupt Request Flag Cleared by Hardware (H) or by Software (S) INT0 0 (Highest Priority) C:0003h H if edge, S if level Timer 0 1 C:000Bh H INT1 2 C:0013h H if edge, S if level Timer 1 3 C:001Bh H Serial Port 4 C:0023h S MP3 Decoder 5 C:002Bh S Audio Interface 6 C:0033h S MMC Interface 7 C:003Bh S Two Wire Controller 8 C:0043h S SPI Controller 9 C:004Bh S A to D Converter 10 C:0053h S Keyboard 11 C:005Bh S Reserved 12 C:0063h - USB 13 C:006Bh S Reserved 14 (Lowest Priority) C:0073h - |
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