MPC5200 datasheet(75/80 Pages) FREESCALE

75 / 80 page

System Design Information

MPC5200 Data Sheet, Rev. 4

Freescale Semiconductor

Figure 54. PORRESET vs. JTAG_TRST

5.4.1.2

Connecting JTAG_TRST

The wiring of the JTAG_TRST depends on the existence of a board-related debug interface (see Table 53

below).

Normally this interface is implemented, using a COP (common on-chip processor) connector. The COP

allows a remote computer system (typically, a PC with dedicated hardware and debugging software) to

access and control the internal operations of the MPC5200.

5.4.2

G2_LE COP/BDM Interface

There are two possibilities to connect the JTAG interface: using it with a COP connector and without a

COP connector.

5.4.2.1

Boards interfacing the JTAG port via a COP connector

The MPC5200 functional pin interface and internal logic provides access to the embedded G2_LE

processor core through the Freescale (formerly Motorola) standard COP/BDM interface. Table 53 gives

the COP/BDM interface signals. The pin order shown reflects only the COP/BDM connector order.

Table 53. COP/BDM Interface Signals

BDM

Pin #

MPC5200

I/O Pin

BDM

Connector

Internal

PullUp/Down

External

PullUp/Down

I/O1

—

GND

—

TEST_SEL_0

ckstp_out

—

KEY

—

HRESET

hreset

10k Pull-Up

—

GND

—

SRESET

sreset

10k Pull-Up

—

N/C

—

JTAG_TMS

tms

100k Pull-Up

10k Pull-Up

JTAG_TRST

PORRESET

required assertion of JTAG_TRST

optional assertion of JTAG_TRST

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