MPC5200 datasheet(34/80 Pages) FREESCALE

34 / 80 page

MPC5200 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

The MPC5200 ATA Host Controller design makes data available coincidentally with the active edge of the

WRITE strobe in PIO and Multiword DMA modes.

•

Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample

setup-time beyond that required by the ATA-4 specification.

•

Data is held unchanged until the next active edge of the WRITE strobe. This gives ample

hold-time beyond that required by the ATA-4 specification.

All ATA transfers are programmed in terms of system clock cycles (IP bus clocks) in the ATA Host

Controller timing registers. This puts constraints on the ATA protocols and their respective timing modes

in which the ATA Controller can communicate with the drive.

Faster ATA modes (i.e., UDMA 0, 1, 2) are supported when the system is running at a sufficient frequency

to provide adequate data transfer rates. Adequate data transfer rates are a function of the following:

•

The MPC5200 operating frequency (IP bus clock frequency)

•

Internal MPC5200 bus latencies

•

Other system load dependent variables

The ATA clock is the same frequency as the IP bus clock in MPC5200. See the MPC5200 User Manual [1].

NOTE

All output timing numbers are specified for nominal 50 pF loads.

Table 27. PIO Mode Timing Specifications

PIO Timing Parameter

Min/Max

(ns)

Mode 0

(ns)

Mode 1

(ns)

Mode 2

(ns)

Mode 3

(ns)

Mode 4

(ns)

SpecID

Cycle Time

min

600

383

240

180

120

A8.1

Address valid to DIOR/DIOW setup

min

A8.2

DIOR/DIOW pulse width 16-bit

8-bit

min

165

290

125

290

100

290

A8.3

t2i

DIOR/DIOW recovery time

min

—

A8.4

DIOW data setup

min

A8.5

DIOW data hold

min

A8.6

DIOR data setup

min

A8.7

DIOR data hold

min

55555

A8.8

DIOR/DIOW to address

valid hold

min

2015101010

A8.9

IORDY setup

max

A8.10

IORDY pulse width

max

1250

A8.11

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