MPC5200 datasheet(30/80 Pages) FREESCALE

30 / 80 page

MPC5200 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

3.3.7.2

Burst Mode

Table 25. Burst Mode Timing

NOTES:

1. Wait States (WS) can be programmed in the Chip Select X Register, Bit field WaitP and WaitX. It can be specified 0 - 65535.

2. Example:

Long Burst is used, this means the CS related BERx and SLB bits of the Chip Select Burst Control Register are set and a

burst on the internal XLB is executed. => LB = 1

Data bus width is 8 bit. => DS = 8

=> 41*2*(32/8) = 32 => ACK is asserted for 32 PCI cycles to transfer one cache line.

Wait State is set to 10. => WS = 10

1+10+32 = 43 => CS is asserted for 43 PCI cycles.

3. ACK is output and indicates the burst.

Sym

Description

Min

Max

Units Notes SpecID

tCSA

PCI CLK to CS assertion

1.8

A7.20

tCSN

PCI CLK to CS negation

1.8

A7.21

CS pulse width

(1+WS+4LB*2*(32/DS))*

tPCIck

(1+WS+4LB*2*(32/DS))

*tPCIck

1,2

A7.22

ADDR valid before CS assertion

tIPBIck

tPCIck

A7.23

ADDR hold after CS negation

-0.7

A7.24

OE assertion before CS assertion

0.4

A7.25

OE negation before CS negation

0.4

A7.26

RW valid before CS assertion

tPCIck

A7.27

RW hold after CS negation

tPCIck

A7.28

DATA setup before rising edge of

PCI

1.8

A7.29

DATA hold after rising edge of PCI

A7.30

t10

DATA hold after CS negation

(DC+1)*tPCIck

A7.31

t11

ACK assertion after CS assertion

(WS+1)*tPCIck

A7.32

t12

ACK negation before CS negation

0.6

A7.33

t13

ACK pulse width

4LB*2*(32/DS)*tPCIck

2,3

A7.34

t14

CS assertion after TS assertion

0.8

A7.35

t15

TS pulse width

tPCIck

A7.36

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