MPC5200 datasheet(28/80 Pages) FREESCALE

28 / 80 page

MPC5200 Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

3.3.7

Local Plus Bus

The Local Plus Bus is the external bus interface of the MPC5200. Maximum eight configurable

Chip-selects are provided. There are two main modes of operation: non-MUXed (Legacy and Burst) and

MUXED. The reference clock is the PCI CLK. The maximum bus frequency is 66 MHz.

Definition of Acronyms and Terms:

WS = Wait State

DC = Dead Cycle

LB = Long Burst

DS = Data size in Byte

tPCIck = PCI clock period

tIPBIck = IPBI clock period

Figure 11. Timing Diagram—IPBI and PCI clock (example ratio: 4:1)

3.3.7.1

Non-MUXed Mode

Table 24. Non-MUXed Mode Timing

Sym

Description

Min

Max

Units

Notes

SpecID

tCSA

PCI CLK to CS assertion

1.8

A7.1

tCSN

PCI CLK to CS negation

1.8

A7.2

CS pulse width

(2+WS)*tPCIck

A7.3

ADDR valid before CS assertion

tIPBIck

tPCIck

A7.4

ADDR hold after CS negation

tIPBIck

-ns

A7.5

OE assertion before CS assertion

0.4

A7.6

OE negation before CS negation

0.4

A7.7

RW valid before CS assertion

tPCIck

-ns

A7.8

RW hold after CS negation

tIPBIck

-ns

A7.9

DATA output valid before CS assertion

tIPBIck

A7.10

DATA output hold after CS negation

tIPBIck

A7.11

t10

DATA input setup before CS negation

2.8

A7.12

t11

DATA input hold after CS negation

(DC+1)*tPCIck

A7.13

t12

ACK assertion after CS assertion

tPCIck

-ns

A7.14

t13

ACK negation after CS negation

tPCIck

A7.15

PCI CLK

IPBI CLK

tIPBIck

tPCIck

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