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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CSG14K_CSG8K датащи(PDF) 38 Page - ams AG |
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CSG14K_CSG8K датащи(HTML) 38 Page - ams AG |
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38 / 113 page  Document Feedback CSG14K_CSG8K Functional Description Datasheet • PUBLIC DS000571 • v1-00 • 2020-Dec-15 112 │ 37 Information Disabling shutter lag matching causes an image artefact when operating the sensor in pipelined mode. This artefact shows up as one bright row in the output image. The location of that row depends on when the pipelined exposure started. Figure 34: State Diagram: Sequential Operation, No Shutter Lag at Start 7.2.7 Sensor Control Modes Figure 35: Control Mode Register Reg.Name Bank Addr Bits Def. Description CTRL_MODE 0 11 [2:0] 0 0: Full external 1: Programmed external 2: Triggered internal 3: Streaming 4: In-line streaming The travel through the state diagrams of Figure 33 and Figure 34 can be externally controlled with the sensor inputs REQ_EXP and REQ_FRAME and a bunch of register settings (which will be detailed in further sections). This can be done in a number of different modes (each varying slightly in behavior and level of dependency on I/O control versus register configuration). EXPOSURE GLOB IDLE RESET READOUT Actual exposure |
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