CSG14K_CSG8K datasheet(97/113 Pages) AMSCO

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 96

The sensor can indicate through status bits when it is not safe to request a new frame/exposure or

when it will be ignored. This coincides with these invalid and special cases described in 7.2.7 :

●

FE_i0, FE_i1, FE_i2, FE_i3

●

PE_i0, PE_s2

●

TI_s2

●

In steaming mode, the status bits indicate that the request will be ignored.

The status bits can be enabled on the CTRL channel or observed on one of the digital test output pins.

Attention

Enabling the not-safe-to-request status bits on the CTRL channel might influence the control word in

idle state. It is therefore recommended

to perform control channel training with EN_NSF set to ‘0’.

7.8.4

Digital Test Output

Figure 122:

Digital Test Output Register

Reg. Name

Bank

Addr

Bits

Description

DMUX1_SEL

50-51

[9:5]

Sets pin TDIG1 function

DMUX2_SEL

50-51

[14:10]

Sets pin TDIG2 function

A number of digital signals of the chip can be monitored in real-time during normal sensor operation

via the sensor output pins TDIG1 to TDIG4. This can be useful for testing and debugging the system

without having to rely on the sub-LVDS implementation of the control channel, so a test pad or

connection to the FPGA is recommended.

Selecting which signal to be monitored is done with DMUX1_SEL registers for TDIG1 (bottom) and

TDIG3 (top) and with DMUX2_SEL registers for TDIG2 (bottom) and TDIG4 (top).

Figure 123:

TDIG Mapping

DMUX*_SEL

Description

PLL lock status

Global sampling phase(1)

Exposure status (group S)

Exposure status (group L)

EOBVAL

SVAL

FVAL

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