CSG14K_CSG8K datasheet(67/113 Pages) AMSCO

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 66

Parameter

Example 1

Example 2

RG_CTRL

Effective data rate(1)

699 Mbit/s

1000 Mbit/s

(1)

The effective data rate is equal to the available bandwidth and does not take into account any overhead data.

As described in section 7.2.2, a PLL lock time of maximum 1 ms needs to be respected. The lock

status of a PLL can be checked by polling the read-only PLL_LOCK register.

The PLL_LOCK registers are only present in the two sequencers. The bottom-side sequencer (with

BLOCK_ID 0) holds the lock information of the bottom-side PLL. The top-side sequencer (with

BLOCK_ID 1) holds the lock information of the top-side PLL.

Figure 73:

PLL Lock Register

Bank

Addr

Read Value

PLL_LOCK

0: PLL out of lock

1: PLL locked

Set Data Interface

The sensor’s pixel data is transmitted over its sub-LVDS output channels. More information on the

output interface and low-level timing can be found in section 7.3.Figure 44 shows the required register

uploads to set the output format.

Figure 74:

Output Format Registers

Bank

Address

Value

OUTP_FORMAT

PLL_WRAP_MAIN_DIV

CLKGEN_BYTE_H

CLKGEN_BYTE_L

A distinction should be made between the amount of used output channels and the amount of active

output channels. The amount of used output channels refers to the amount of channels that is used for

full horizontal ROI readout. The amount of active output channels refers to the amount of channels

that are actively outputting pixel data. Depending on the horizontal ROI settings, the amount of active

channels is either equal to or less than the amount of used output channels. More information on

configuring the horizontal ROI can be found in section 7.5.4.

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