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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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CSG14K_CSG8K датащи(PDF) 70 Page - ams AG |
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CSG14K_CSG8K датащи(HTML) 70 Page - ams AG |
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70 / 113 page  Document Feedback CSG14K_CSG8K Functional Description Datasheet • PUBLIC DS000571 • v1-00 • 2020-Dec-15 112 │ 69 # Register Bank Address Value 4 - 3 96 241 5 - - 1 0 6 - 3 96 243 7 EN_ADC_RST_N 1 101 1 8 EN_CLK_ADC 1 100 1 Assert Soft Reset To return the sensor to the soft reset state, the following register uploads need to be applied. Figure 79: Assert Soft Reset Sequence # Register Bank Address Value 1 CMD_REGS 0 6 0 2 EN_CLK_MAIN 0 90 0 3 - - 1 1 4 - 3 96 240 5 - - 1 0 6 - 3 96 240 7 EN_ADC_RST_N 1 101 0 8 EN_CLK_ADC 1 100 0 Asserting the soft reset does not affect the PLL. However, internal clock generation and distribution are disabled when the soft reset is asserted. The soft reset has to be released again before any frames can be grabbed. Attention Asserting the soft reset stops the output drivers. Any phase alignment done by the external system is lost and should be redone when the soft reset is released. Set ROI Refer to section 7.5.3 for details on configuring the vertical ROI. Refer to section 7.5.4 for details on configuring the horizontal ROI. In case of operation in IMG.3 (10-bit small window mode), the following sequence of SPI writes is required for correct sensor configuration. |
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