CSG14K_CSG8K datasheet(25/113 Pages) AMSCO

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 24

Figure 16:

Power-Up Sequence (not to scale)

7.2.3

Clocking

The sensor has two CMOS clock inputs: SPI_CLK and CLK_IN. SPI_CLK is part of the SPI interface

used to configure the sensor. All other internal sensor clocks are derived from the PLL running on

CLK_IN.

Refer to section 5 for the electrical specifications of the input clocks and to section 7.4.3 for the

configuration procedure of the PLL.

7.2.4

SPI and Register Access

The sensor operation must be configured by uploading register settings. These static register values

control the behavior of the sequencer on the chip, but also of all the analog and mixed-signal blocks.

To write and read register settings the SPI interface is used.

The SPI (Serial Peripheral Interface) consists of four wires, as shown in Figure 17.

The CSG14K_CSG8K image sensor always operates as the SPI slave. A single SPI access always

consists of:

●

Transfer of a control bit from master to slave to specify the transfer direction (read or write).

●

Transfer of 7-bit register address from master to slave.

●

Transfer of 8-bit data from master to slave (write operation) or from slave to master (read

operation).

Figure 17:

SPI Signal Overview

Pin Name

Direction

Purpose

SPI_CSN

Sensor Input

Active-low chip select

VDD33*, VDD12*, VDDPIX

VDD45, VSSNEG

CLK_IN

RST_N

SPI

PLL_LOCK

REQ_EXP

sensor state

1µs

1ms

1µs

soft reset

hard reset

idle

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