CSG14K_CSG8K datasheet(28/113 Pages) AMSCO

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CSG14K_CSG8K

Functional Description

Datasheet

• PUBLIC

DS000571

• v1-00 • 2020-Dec-15

112

│ 27

SPI Write

All data bits on SPI_MOSI are sampled by the sensor on the rising edge of SPI_CLK. The chip-select

signal, SPI_CSN, shall be low at least ½ of an SPI_CLK period before the first data bit is sampled.

SPI_CSN shall remain low for at least ½ of an SPI_CLK period after the last falling edge of SPI_CLK.

The first bit transferred is a control bit indicating a write operation (‘1’). Both the subsequent address

(A<6:0>) and data (D<7:0>) are sent MSB-first.

When writing multiple sequential registers (e.g. 100, 101, 102 ...), the write burst mode can be used.

The address is that of the first register to be written to and the sequencer will automatically shift to the

next register after 8 data bits. SPI_CSN shall stay low the entire time.

The actual register value is updated with the new value on the falling edge of SPI_CLK on every D[0]

bit. I.e. SPI_CLK shall go low at the end of D[0] for the write sequence to be completed. The timing of

both write modes is illustrated below.

Figure 21:

SPI Write Timing

SPI Read

The timing of the SPI read sequence is similar to the SPI write sequence. The main differences are

the control bit and the use of SPI_MISO. An SPI read is indicated by setting the control bit to ‘0’. After

the control bit, the address of the register to read shall be transmitted MSB first. At the end of the LSB

of the address, the data is launched on the SPI_MISO pin on the falling edge of the SPI_CLK. This

means that the data can be sampled by the SPI master on the rising edge of the SPI_CLK. The data

D<7:0> is transmitted MSB first on SPI_MISO. When not transmitting data, the SPI_MISO output is in

high-Z state.

Sequential SPI register addresses can also be read out in burst mode by keeping SPI_CSN low and

clocking out additional bytes. The timing of both read modes is illustrated below.

’1'

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

ctrl

address

data (N)

Hi-Z

Internal reg updated

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

data (N+1)

Internal reg updated

’1'

A[6]

A[5]

A[4]

A[3]

A[2]

A[1]

A[0]

D[7]

D[6]

D[5]

D[4]

D[3]

D[2]

D[1]

D[0]

ctrl

address

data

Hi-Z

Internal reg updated

Tspi

SPI_CLK

SPI_CSN

SPI_MOSI

SPI_MISO

SPI_CLK

SPI_CSN

SPI_MOSI

SPI_MISO

½ Tspi

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