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CSG14K_CSG8K датащи(PDF) 78 Page - ams AG |
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CSG14K_CSG8K датащи(HTML) 78 Page - ams AG |
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78 / 113 page ![]() Document Feedback CSG14K_CSG8K Functional Description Datasheet • PUBLIC DS000571 • v1-00 • 2020-Dec-15 112 │ 77 Equation 9: ������������ℎ������������������������������_������������������ = 32 ∗ ������������������������_������������������ Disabling shutter lag is not possible in the 10-bit short exposure more (IMG.2) and the 12-bit short exposure mode (IMG.5). 7.5.2 Row Length Figure 91: Row Length Register Register Name Bank Addr Bits Description ROW_LENGTH 4 18-19 [13:0] See below The row length trow defines the DVAL frequency during readout; it can be programmed in number of CLK_PIX cycles with the ROW_LENGTH register. The row length has a minimum value because a number of parallel processes in the sensor need to be completed within one row time. The minimal row length depends on the number of outputs used (see equations in section 7.4.3). The maximal row length value is only constrained by the 14 bits size of register. Fine frame rate adjustments are done through external timing or with the FRAME_TIME register. Changing the row length only influences the DVAL frequency within a readout sequence. This can be useful when smaller or slower row buffers are used in the external system. An exception to this rule is the in-line streaming mode, where the ROW_LENGTH register does directly alter the frame rate. 7.5.3 Vertical Windowing The sensor supports multiple windows in the vertical direction to create regions of interest (ROI). Row Addressing As introduced in section 7.1.1, the sensor has buffer pixels rows above and below the effective pixels. Every row in the array is paired with a physical row address. This row address is used to specify vertical ROI positions as described in next section. Row addresses are assigned in ascending order starting from 0 for the row closest to the package pin row 1. |
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