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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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S71GS256 датащи(PDF) 104 Page - SPANSION |
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S71GS256 датащи(HTML) 104 Page - SPANSION |
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104 / 195 page  104 CellularRAM Type 2 cellRAM_00_A0 October 4, 2004 Advan ce In form ati o n that part of the DRAM array that contains essential data. Temperature compen- sated refresh (TCR) adjusts the refresh rate to match the device temperature— the refresh rate decreases at lower temperatures to minimize current consump- tion during standby. Deep power-down (DPD) enables the system to halt the refresh operation altogether when no vital information is stored in the device. The system-configurable refresh mechanisms are accessed through the RCR. Note: Functional block diagrams illustrate simplified device operation. See truth table, ball descriptions, and timing di- agrams for detailed information. Figure 21. Functional Block Diagram 128M: A[22:0] 64M: A[21:0] 32M: A[20:0] Input/ Output MUX and Buffers Control Logic DRAM MEMORY ARRAY CE# WE# OE# CLK ADV# CRE WAIT LB# UB# DQ[7:0] DQ[15:8] Address Decode Logic Refresh Configuration Register (RCR) Bus Configuration Register (BCR) |
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