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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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S71GS256 датащи(PDF) 94 Page - SPANSION |
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S71GS256 датащи(HTML) 94 Page - SPANSION |
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94 / 195 page  94 S29GLxxxN MirrorBitTM Flash Family S29GLxxxN_MCP_A1 December 15, 2004 Advan ce In form ati o n AC Characteristics Hardware Reset (RESET#) Notes: 1. Not 100% tested. If ramp rate is equal to or faster than 1V/100µs with a falling edge of the RESET# pin initiated, the RESET# pin needs to be held low only for 100µs for power-up. 2. Next generation devices may have different reset speeds. Parameter Description Speed (Note 2) Unit JEDEC Std. tReady RESET# Pin Low (During Embedded Algorithms) to Read Mode (See Note) Max 20 ns tReady RESET# Pin Low (NOT During Embedded Algorithms) to Read Mode (See Note) Max 500 ns tRP RESET# Pulse Width Min 500 ns tRH Reset High Time Before Read (See Note) Min 50 ns tRPD RESET# Low to Standby Mode Min 20 µs tRB RY/BY# Recovery Time Min 0 ns RESET# RY/BY# RY/BY# tRP tReady Reset Timings NOT during Embedded Algorithms tReady CE#, OE# tRH CE#, OE# Reset Timings during Embedded Algorithms RESET# tRP tRB tRH Figure 13. Reset Timings |
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