S71GS256 datasheet(25/195 Pages) SPANSION

25 / 195 page

December 15, 2004 S29GLxxxN_MCP_A1

S29GLxxxN MirrorBitTM Flash Family

Ad vance

Info rmat i o n

If the system asserts VHH on this pin, the device automatically enters the afore-

mentioned Unlock Bypass mode, temporarily unprotects any protected sector

groups, and uses the higher voltage on the pin to reduce the time required for

program operations. The system would use a two-cycle program command se-

quence as required by the Unlock Bypass mode. Removing VHH from the WP#/

ACC pin returns the device to normal operation. Note that the WP#/ACC pin must

not be at VHH for operations other than accelerated programming, or device dam-

age may result. WP# has an internal pullup; when unconnected, WP# is at VIH.

Autoselect Functions

If the system writes the autoselect command sequence, the device enters the au-

toselect mode. The system can then read autoselect codes from the internal

cycle timings apply in this mode. Refer to the “Autoselect Mode” section on page

52 and “Autoselect Command Sequence” section on page 66 sections for more

information.

Standby Mode

When the system is not reading or writing to the device, it can place the device

in the standby mode. In this mode, current consumption is greatly reduced, and

the outputs are placed in the high impedance state, independent of the OE#

input.

The device enters the CMOS standby mode when the CE# and RESET# pins are

both held at VIO ± 0.3 V. (Note that this is a more restricted voltage range than

VIH.) If CE# and RESET# are held at VIH, but not within VIO ± 0.3 V, the device

will be in the standby mode, but the standby current will be greater. The device

requires standard access time (tCE) for read access when the device is in either

of these standby modes, before it is ready to read data.

If the device is deselected during erasure or programming, the device draws ac-

tive current until the operation is completed.

Refer to the “DC Characteristics” section on page 90 for the standby current

specification.

Automatic Sleep Mode

The automatic sleep mode minimizes Flash device energy consumption. The de-

vice automatically enables this mode when addresses remain stable for tACC +

30 ns. The automatic sleep mode is independent of the CE#, WE#, and OE# con-

trol signals. Standard address access timings provide new data when addresses

are changed. While in sleep mode, output data is latched and always available to

the system. Refer to the “DC Characteristics” section on page 90 for the

automatic sleep mode current specification.

RESET#: Hardware Reset Pin

The RESET# pin provides a hardware method of resetting the device to reading

array data. When the RESET# pin is driven low for at least a period of tRP, the

device immediately terminates any operation in progress, tristates all output

pins, and ignores all read/write commands for the duration of the RESET# pulse.

The device also resets the internal state machine to reading array data. The op-

eration that was interrupted should be reinitiated once the device is ready to

accept another command sequence, to ensure data integrity.

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