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S71GS256 датащи(PDF) 102 Page - SPANSION

номер детали S71GS256
подробное описание детали  128N based MCPs
PDF  195 Pages
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S71GS256 датащи(HTML) 102 Page - SPANSION

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102
S29GLxxxN MirrorBitTM Flash Family
S29GLxxxN_MCP_A1 December 15, 2004
Advan ce
In form ati o n
Erase And Programming Performance
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V VCC, 10,000 cycles, checkerboard
pattern.
2. Under worst case conditions of 90°C, VCC = 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 16-word write buffer operation.
4. The typical chip programming time is considerably less than the maximum chip programming time listed, since most
words program faster than the maximum program times listed.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program
command. See Table 12 for further information on command definitions.
TSOP Pin and BGA Package Capacitance
Notes:
1. Sampled, not 100% tested.
2. Test conditions TA = 25°C, f = 1.0 MHz.
Parameter
Typ
(Note 1)
Max
(Note 2)
Unit
Comments
Sector Erase Time
0.5
3.5
sec
Excludes 00h
programming prior to
erasure (Note 5)
Chip Erase Time
S29GL128N
64
256
sec
S29GL256N
128
512
S29GL512N
256
1024
Total Write Buffer
Programming Time
(Note 3)
240
µs
Excludes system level
overhead (Note 6)
Total Accelerated Effective
Write Buffer Programming
Time (Note 3)
200
µs
Chip Program Time
S29GL128N
123
sec
S29GL256N
246
S29GL512N
492
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
CIN
Input Capacitance
VIN = 0
TSOP
6
7.5
pF
BGA
4.2
5.0
pF
COUT
Output Capacitance
VOUT = 0
TSOP
8.5
12
pF
BGA
5.4
6.5
pF
CIN2
Control Pin Capacitance
VIN = 0
TSOP
7.5
9
pF
BGA
3.9
4.7
pF



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