S71GS256 datasheet(75/195 Pages) SPANSION

75 / 195 page

December 15, 2004 S29GLxxxN_MCP_A1

S29GLxxxN MirrorBitTM Flash Family

Ad vance

Info rmat i o n

gram operation using the DQ7 or DQ6 status bits, just as in the standard word

program operation. Refer to the Write Operation Status section for more

information.

In the erase-suspend-read mode, the system can also issue the autoselect com-

mand sequence. Refer to the “Autoselect Mode” section and “Autoselect

Command Sequence” section on page 66 sections for details.

To resume the sector erase operation, the system must write the Erase Resume

command. The address of the erase-suspended sector is required when writing

this command. Further writes of the Resume command are ignored. Another

Erase Suspend command can be written after the chip has resumed erasing. It is

important to allow an interval of at least 5 ms between Erase Resume and Erase

Suspend.

Lock Register Command Set Definitions

The Lock Register Command Set permits the user to one-time program the Se-

cured Silicon Sector Protection Bit, Persistent Protection Mode Lock Bit, and

Password Protection Mode Lock Bit. The Lock Register bits are all readable after

an initial access delay.

The Lock Register Command Set Entry command sequence must be issued

prior to any of the following commands listed, to enable proper command

execution.

Note that issuing the Lock Register Command Set Entry command disables

reads and writes for the flash memory.

Lock Register Program Command

Lock Register Read Command

The Lock Register Command Set Exit command must be issued after the ex-

ecution of the commands to reset the device to read mode. Otherwise the device

will hang. If this happens, the flash device must be reset. Please refer to RESET#

for more information. It is important to note that the device will be in either Per-

sistent Protection mode or Password Protection mode depending on the mode

selected prior to the device hang.

For either the Secured Silicon Sector to be locked, or the device to be perma-

nently set to the Persistent Protection Mode or the Password Protection Mode, the

associated Lock Register bits must be programmed. Note that the Persistent

Protection Mode Lock Bit and Password Protection Mode Lock Bit can

never be programmed together at the same time. If so, the Lock Register

Program operation will abort.

The Lock Register Command Set Exit command must be initiated to re-

enable reads and writes to the main memory.

Password Protection Command Set Definitions

The Password Protection Command Set permits the user to program the 64-bit

password, verify the programming of the 64-bit password, and then later unlock

the device by issuing the valid 64-bit password.

The Password Protection Command Set Entry command sequence must be

issued prior to any of the commands listed following to enable proper command

execution.

Note that issuing the Password Protection Command Set Entry command

disabled reads and writes the main memory.

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