S71GS256 datasheet(24/195 Pages) SPANSION

24 / 195 page

S29GLxxxN MirrorBitTM Flash Family

S29GLxxxN_MCP_A1 December 15, 2004

Advan ce

In form ati o n

content occurs during the power transition. No command is necessary in this

mode to obtain array data. Standard microprocessor read cycles that assert valid

addresses on the device address inputs produce valid data on the device data

outputs. The device remains enabled for read access until the command register

contents are altered.

See “Reading Array Data” on page 66 for more information. Refer to the AC Read-

Only Operations table for timing specifications and to Figure 11 for the timing di-

agram. Refer to the DC Characteristics table for the active current specification

on reading array data.

Page Mode Read

The device is capable of fast page mode read and is compatible with the page

mode Mask ROM read operation. This mode provides faster read access speed for

random locations within a page. The page size of the device is 8 words/16 bytes.

The appropriate page is selected by the higher address bits A(max)–A3. Address

bits A2–A0 determine the specific word within a page. This is an asynchronous

operation; the microprocessor supplies the specific word location.

The random or initial page access is equal to tACC or tCE and subsequent page

read accesses (as long as the locations specified by the microprocessor falls

within that page) is equivalent to tPACC. When CE# is de-asserted and reasserted

for a subsequent access, the access time is tACC or tCE. Fast page mode accesses

are obtained by keeping the “read-page addresses” constant and changing the

“intra-read page” addresses.

Writing Commands/Command Sequences

To write a command or command sequence (which includes programming data

to the device and erasing sectors of memory), the system must drive WE# and

CE# to VIL, and OE# to VIH.

The device features an Unlock Bypass mode to facilitate faster programming.

Once the device enters the Unlock Bypass mode, only two write cycles are re-

quired to program a word or byte, instead of four. The “Word Program Command

Sequence” section has details on programming data to the device using both

standard and Unlock Bypass command sequences.

An erase operation can erase one sector, multiple sectors, or the entire device.

Table 2, Table 4, and Table 5 indicate the address space that each sector occupies.

Refer to the DC Characteristics table for the active current specification for the

write mode. The AC Characteristics section contains timing specification tables

and timing diagrams for write operations.

Write Buffer

Write Buffer Programming allows the system write to a maximum of 16 words/32

bytes in one programming operation. This results in faster effective programming

time than the standard programming algorithms. See “Write Buffer” for more

information.

Accelerated Program Operation

The device offers accelerated program operations through the ACC function. This

is one of two functions provided by the WP#/ACC pin. This function is primarily

intended to allow faster manufacturing throughput at the factory.

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