MCF5373CAB180 datasheet(19/42 Pages) FREESCALE

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Preliminary Electrical Characteristics

MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

5.4.3.1

Power Up Sequence

If EVDD/SDVDD are powered up with IVDD at 0 V, then the sense circuits in the I/O pads will cause all

pad output drivers connected to the EVDD/SDVDD to be in a high impedance state. There is no limit on

how long after EVDD/SDVDD powers up before IVDD must powered up. IVDD should not lead the EVDD,

SDVDD or PLLVDD by more than 0.4 V during power ramp-up, or there will be high current in the internal

ESD protection diodes. The rise times on the power supplies should be slower than 1

µs to avoid turning

on the internal ESD protection clamp diodes.

The recommended power up sequence is as follows:

1. Use 1

µs or slower rise time for all supplies.

2. IVDD/PLLVDD and EVDD/SDVDD should track up to 0.9 V, then separate for the completion of

ramps with EVDD/SD VDD going to the higher external voltages. One way to accomplish this is to

use a low drop-out voltage regulator.

5.4.3.2

Power Down Sequence

If IVDD/PLLVDD are powered down first, then sense circuits in the I/O pads will cause all output drivers

to be in a high impedance state. There is no limit on how long after IVDD and PLLVDD power down before

EVDD or SDVDD must power down. IVDD should not lag EVDD, SDVDD, or PLLVDD going low by more

than 0.4 V during power down or there will be undesired high current in the ESD protection diodes. There

are no requirements for the fall times of the power supplies.

The recommended power down sequence is as follows:

1. Drop IVDD/PLLVDD to 0 V.

2. Drop EVDD/SDVDD supplies.

5.5

Power Consumption Specifications

Estimated maximum RUN mode power consumption measurements are shown in the below figure.

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