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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCF5373CAB180 датащи(PDF) 23 Page - Freescale Semiconductor, Inc |
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MCF5373CAB180 датащи(HTML) 23 Page - Freescale Semiconductor, Inc |
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23 / 42 page  Preliminary Electrical Characteristics MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3 Preliminary Freescale Semiconductor 23 Figure 11. FlexBus Read Timing. Table 10. FlexBus AC Timing Specifications Num Characteristic Symbol Min Max Unit Notes Frequency of Operation — 80 Mhz fsys/3 FB1 Clock Period (FB_CLK) tFBCK — 12.5 ns tcyc FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) tFBCHDCV —7.0 ns 1 NOTES: 1 Timing for chip selects only applies to the FB_CS[5:0] signals. Please see Section 5.8.2, “DDR SDRAM AC Timing Characteristics” for SD_CS[3:0] timing. FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], and OE) tFBCHDCI 1— ns 1, 2 2 The FlexBus supports programming an extension of the address hold. Please consult the MCF5373 Reference Manual for more information. FB4 Data Input Setup tDVFBCH 3.5 — ns FB5 Data Input Hold tDIFBCH 0— ns FB6 Transfer Acknowledge (TA) Input Setup tCVFBCH 4— ns FB7 Transfer Acknowledge (TA) Input Hold tCIFBCH 0— ns FB8 Address Output Valid (A[23:0]) tFBCHAV —6.0 ns 3 3 These specs are used when the A[23:0] signals are configured as 23-bit, non-muxed FlexBus address signals. FB9 Address Output Hold (A[23:0]) tFBCHAI 1— ns FB_CLK A[23:0] D[31:0] R/W TS FB_CSn OE TA FB1 A[23:0] FB2 FB3 FB4 FB5 FB6 FB7 DATA BE/BWEn |
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