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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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MCF5373CAB180 датащи(PDF) 24 Page - Freescale Semiconductor, Inc |
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MCF5373CAB180 датащи(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 42 page  MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3 Preliminary Preliminary Electrical Characteristics Freescale Semiconductor 24 Figure 12. Flexbus Write Timing 5.8 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not support both at the same time. 5.8.1 SDR SDRAM AC Timing Characteristics The following timing numbers indicate when data will be latched or driven onto the external bus, relative to the memory bus clock, when operating in SDR mode on write cycles and relative to SD_DQS on read cycles. The device’s SDRAM controller is a DDR controller that has an SDR mode. Because it is designed to support DDR, a DQS pulse must still be supplied to device for each data beat of an SDR read. Te processor accomplishes this by asserting a signal named SD_DQS during read cycles. Care must be taken during board design to adhere to the following guidelines and specs with regard to the SDR_DQS signal and its usage. Table 11. SDR Timing Specifications Symbol Characteristic Symbol Min Max Unit Notes Frequency of Operation TBD 80 Mhz 1 SD1 Clock Period tSDCK 12.5 TBD ns 2 SD2 Clock Skew tSDSK —TBD SD3 Pulse Width High tSDCKH 0.45 0.55 SD_CLK 3 FB_CLK A[23:0] D[31:0] R/W TS FB_CSn TA FB1 FB2 FB3 FB3 FB6 FB7 OE BE/BWEn |
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