Preliminary Electrical Characteristics

Preliminary

Freescale Semiconductor

27

5.8.2

DDR SDRAM AC Timing Characteristics

When using the SDRAM controller in DDR mode, the following timing numbers must be followed to

properly latch or drive data onto the memory bus. All timing numbers are relative to the four DQS byte

lanes. The following timing numbers are subject to change at anytime, and are only provided to aid in early

board design. Please contact your local Freescale representative if questions develop.

Table 12. DDR Timing Specifications

Num

Characteristic

Symbol

Min

Max

Unit

Notes

Frequency of Operation

80

TBD

Mhz

1

NOTES:

1

The frequency of operation is either 2x or 4x the FB_CLK frequency of operation. FlexBus and SDRAM clock operate at the

same frequency as the internal bus clock.

DD1

Clock Period

TBD

12.5

ns

2

2

SD_CLK is one SDRAM clock in (ns).

DD2

Pulse Width High

0.45

0.55

SD_CLK

3

3

Pulse width high plus pulse width low cannot exceed min and max clock period.

DD3

Pulse Width Low

0.45

0.55

SD_CLK

3

DD4

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Valid

—0.5

× SD_CLK

+1.0

ns

4

4

Command output valid should be 1/2 the memory bus clock (SD_CLK) plus some minor adjustments for process,

temperature, and voltage variations.

DD5

Address, SD_CKE, SD_CAS, SD_RAS, SD_WE,

SD_CS[1:0] - Output Hold

2.0

—

ns

DD6

Write Command to first DQS Latching Transition

—

1.25

SD_CLK

DD7

Data and Data Mask Output Setup (DQ-->DQS)

Relative to DQS (DDR Write Mode)

1.5

—

ns

5

6

5

This specification relates to the required input setup time of today’s DDR memories. Rigoletto’s output setup should be larger

than the input setup of the DDR memories. If it is not larger, then the input setup on the memory will be in violation.

MEM_DATA[31:24] is relative to MEM_DQS[3], MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to

MEM_DQS[1], and MEM_[7:0] is relative MEM_DQS[0].

6

The first data beat will be valid before the first rising edge of DQS and after the DQS write preamble. The remaining data

beats will be valid for each subsequent DQS edge.

DD8

Data and Data Mask Output Hold (DQS-->DQ)

Relative to DQS (DDR Write Mode)

1.0

—

ns

7

7

This specification relates to the required hold time of today’s DDR memories. MEM_DATA[31:24] is relative to MEM_DQS[3],

MEM_DATA[23:16] is relative to MEM_DQS[2], MEM_DATA[15:8] is relative to MEM_DQS[1], and MEM_[7:0] is relative

MEM_DQS[0].

DD9

Input Data Skew Relative to DQS (Input Setup)

—1

ns

8

DD10 Input Data Hold Relative to DQS.

0.25

× SD_CLK

+0.5ns

—ns

9

0.5

—

ns

DD12 DQS input read preamble width

0.9

1.1

SD_CLK

DD13 DQS input read postamble width

0.4

0.6

SD_CLK

DD14 DQS output write preamble width

0.25

SD_CLK

DD15 DQS output write postamble width

0.4

0.6

SD_CLK