MCF5373CAB180 datasheet(33/42 Pages) FREESCALE

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Preliminary Electrical Characteristics

MCF5373 ColdFire® Microprocessor Data Sheet, Rev. 0.3

Preliminary

Freescale Semiconductor

Figure 21 shows timing for the values in Table 17 and Table 16.

Figure 21. I2C Input/Output Timings

5.14 Fast Ethernet AC Timing Specifications

MII signals use TTL signal levels compatible with devices operating at either 5.0 V or 3.3 V.

5.14.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV,

FEC_RXER, and FEC_RXCLK)

The receiver functions correctly up to a FEC_RXCLK maximum frequency of 25 MHz +1%. There is no

minimum frequency requirement. In addition, the processor clock frequency must exceed twice the

FEC_RXCLK frequency.

Table 18 lists MII receive channel timings.

Figure 22 shows MII receive signal timings listed in Table 18.

NOTES:

Output numbers depend on the value programmed into the IFDR; an IFDR programmed with the maximum

frequency (IFDR = 0x20) results in minimum output timings as shown in Table 17. The I2C interface is

designed to scale the actual data transition time to move it to the middle of the SCL low period. The actual

position is affected by the prescale and division values programmed into the IFDR; however, the numbers

given in Table 17 are minimum values.

Because I2C_SCL and I2C_SDA are open-collector-type outputs, which the processor can only actively

drive low, the time I2C_SCL or I2C_SDA take to reach a high level depends on external signal capacitance

and pull-up resistor values.

Specified at a nominal 50-pF load.

Table 18. MII Receive Signal Timing

Num

Characteristic

Min

Max

Unit

FEC_RXD[3:0], FEC_RXDV, FEC_RXER to FEC_RXCLK setup

—

FEC_RXCLK to FEC_RXD[3:0], FEC_RXDV, FEC_RXER hold

—

FEC_RXCLK pulse width high

35%

65%

FEC_RXCLK period

FEC_RXCLK pulse width low

35%

65%

FEC_RXCLK period

I2C_SCL

I2C_SDA

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