ISL98607

5. General Layout Guidelines

FN8421 Rev.1.00

Page 24 of 29

Jun.3.19

5.

General Layout Guidelines

When designing the printed circuit board (PCB) layout for the ISL98607, it is very important to understand the

power requirements of the system. Some general best practices should be adhered to create an optimal PCB

layout:

1. Careful consideration should be taken with any traces carrying AC signals. Keep AC current loops as short and

as tight as possible. The current loop generates a magnetic field, which can couple to another conductor,

inducing unwanted voltage. Place components such that current flows through them in a straight line as much

as possible, which helps reduce the loop sizes and the EMI from the PCB.

2. If trace lengths are long, the resistance of the trace increases, can cause some reduction in IC efficiency, and

cause system instability. Make the traces carrying power wide and short.

3. In discontinuous conduction mode, the direction of the current is interrupted every few cycles. This may result

in large di/dt (transient load current). When injected in the ground plane the current may cause voltage drops,

which can interfere with sensitive circuitry. Connect the analog ground and power ground of the IC very close

to the IC to mitigate this issue.

4. One plane/layer in the PCB is recommended to be a dedicated ground plane. A large area of metal will have

lower resistance, which reduces the return current impedance. More ground plane area minimizes parasitics

and avoids corruption of the ground reference.

5. Isolate low frequency digital signals from any high frequency signals generated by switching frequency and

harmonics. PCB traces should not cross each other. If they must cross due to the layout restriction, they must

cross perpendicularly to reduce the magnetic field interaction.

6. The amount of copper that should be poured (thickness) depends upon the power requirement of the system.

Insufficient copper increases resistance of the PCB, which increases heat dissipation.

7. Generally, vias should not be used to route high current paths.

8. While designing the layout of switched controllers, do not use the auto routing function of the PCB layout

software. Auto routing connects the nets with same electrical name and does not account for ideal trace

lengths and positioning.

5.1

ISL98607 Specific Layout Guidelines

1. Connect the input capacitor to the VIN pin with the smallest trace possible. This helps reject high frequency

disturbances and promotes good regulation of the VBST, VP, and VN regulators.

2. Connect the boost inductor to the LXP pin with a short and wide trace. Careful consideration should be made

in selecting the inductor as it may cause electromagnetic interference, which could affect IC functionality. A

shielded inductor is recommended.

3. The device has VBST and VBSTCP pins. VBST is the output of the boost regulator and VBSTCP is the input

for the negative charge pump. Connect and short VBST and VBSTCP to each other on the PCB with a short

and thick trace to avoid parasitic inductance and resistance. A 10µF/10V capacitor should be used on VBST.

The distance of the capacitor from the VBST and VBSTCP pin is critical (it should be placed very close to the

IC with a short and thick trace).

4. Renesas highly recommends that VN and VSUB are shorted together with a short and thick trace. It is

recommended that 2x10µF/10V capacitors are placed on VN to minimize output ripple. Additionally, it helps

minimize noise that may be coupled from the high-frequency ripple of the charge pump.

5. The VP regulator has two output pins (VP). Connect both pins directly with a short and thick trace.

6. Connect the IC Analog ground (AGND) and power ground (PGND) to each other. It is crucial to connect/short

these two grounds very close to the IC.

7. Isolate the digital input pins, ENN and ENP, from the high di/dt and dv/dt signals. Otherwise, it may cause a

glitch on those inputs.

8. I2C signals, if not used, should be tied to VIN.