ISL98607

4. Application Information

FN8421 Rev.1.00

Page 12 of 29

Jun.3.19

4.1.7 Device Address and R/W Bit

Data transfers follow the format shown in Figures 15 and 16. After a valid Start condition, the first byte sent in a

transaction contains the 7-bit Device (Slave) Address plus a direction (R/W) bit. The Device Address identifies

which device (of up to 127 devices on the I2C bus) the Master wishes to communicate with.

After a Start condition, the ISL98607 monitors the first 8 bits (Device Address Byte) and checks for its 7-bit Device

Address in the MSBs. If it recognizes the correct Device Address, it acknowledges and becomes ready for further

communication. If it does not see its Device Address, it sits idle until another Start condition is issued on the bus.

To access the ISL98607, the 7-bit Device Address is 0x29 (0101001x), located in MSB bits <b7:b1>. The 8th bit of

the Device Address byte (LSB bit <b0>) indicates the direction of transfer, READ or WRITE (R/W). A “0” indicates

a WRITE operation (the Master transmits data to the ISL98607 (receiver)). A “1” indicates a Read operation (the

Master receives data from the ISL98607 (transmitter)), see Figure 14.

4.2

Write Operation

A WRITE sequence requires an I2C Start condition, followed by a valid Device Address Byte with the R/W bit set

to ‘0’, a valid Register Address Byte, a Data Byte, and a Stop condition. After each valid byte is sent, the ISL98607

(slave) responds with an ACK. When the Write transaction is completed, the Master should generate a Stop

condition. For sent data to be latched by the ISL98607, the Stop condition should occur after a full byte (8-bits) is

sent and ACK. If a Stop is generated in the middle of a byte transaction, the data is ignored. See Figure 15 for the

ISL98607 I2C Write protocol.

4.3

Read Operation

A READ sequence requires the Master to first write to the ISL98607 to indicate the Register Address/pointer to

read from. Send a Start condition, followed by a valid Device Address Byte with the R/W set to ‘0’, and then a valid

Register Address Byte. Then the Master generates either a Repeat Start condition, or a Stop condition followed by

a new Start condition, and a valid Device Address Byte with the R/W bit set to ‘1’. Finally, the ISL98607 is ready to

send data to the Master from the requested Register Address.

The ISL98607 sends out the Data Byte by asserting control of the SDA pin while the Master generates clock

pulses on the SCL pin. When transmission of the desired data is complete, the Master generates a NACK

condition followed by a Stop condition, and this completes the I2C Read sequence. See Figure 16 on page 13 for

the ISL98607 I2C Read protocol.

Figure 14. Device Address Byte Format

Figure 15. I2C Write Timing Diagram

1

0

1

0

R/W

1

0

0

Read = 1

Write = 0

Device Address = 0x29

B7

B6

B5

B4

B3

B2

B1

B0

Write Data

SDA

(from Master)

SDA

(from Slave)

SCL

(from Master)

76543 2 1 0

A

A 76 5 4 3 2 10

Start

Device Address W

Register Pointer

76 5 4 3 2 10

A 76 5 4 3 2 10 A

Data

Stop

A

A

76 5 4 3 2 10

76543 2 1 0

Device Address = 0x29