ISL98607

4. Application Information

FN8421 Rev.1.00

Page 19 of 29

Jun.3.19

The integrated discharge resistors on the VP and VN outputs are 80Ω (typical) and a 35Ω (typical), respectively. If

the same output capacitor (value, size, rating) is used for VN and VP, the VN rail discharges faster than VP if they

are both turned off at the same time, which is ideal for applications that require the VN rail to go down before VP

at power-OFF.

4.14 Enable Timing Control Options

Three ways to control enable sequencing of the VP and VN regulators are:

•I2C control

• Dual GPIO control

• Single GPIO control

4.14.1 I2C Control

By using I2C, the sequencing of the VP and VN regulator is controlled by writing to the register 0x05. Bit <b1>

controls the VN regulator and <b2> controls the VP regulator. Setting the bits to ‘1’ enables the regulator and

setting to ‘0’ shuts off/disables the regulator. Delaying the writes for setting bit <b1> and <b2> (using separate I2C

transactions) delays the turn-on and turn-off sequence of VP and VN accordingly.

Figure 22 on page 20 shows a 4ms delay between when VP and VN turn on. The 4ms time is an example delay to

show the power-ON sequencing possibility through I2C. This delay is set between the separate I2C writes to set

the enable bits in register 0x05. If both enable bits were set to ‘1’ in the same I2C transaction (same byte), and

ENN and ENP are HIGH, both VP and VN regulators start at the same time (when the data is latched at the Stop

condition).

Figure 23 shows a 2.5ms delay between the VP and VN turn off. The 2.5ms time is an example delay to show the

power-OFF sequencing possibility using I2C.

Figures 24 (zoom in) and 25 (zoom out) on page 20 show a typical I2C data transfer to the ENABLE register. In

this example, VP and VN regulators are enabled by writing data 0x07 to register address 0x05. The VP regulator

is enabled first after the I2C Stop condition, followed by the VN regulator after the internal 2ms delay.

Figure 20. Power-Off Sequence - Activated by ENP and

ENN When VIN is Above UVLO

Figure 21. Power-Off Sequence - Activated by VIN Falling

Below UVLO

VIN

UVLO

ENP

VBST

ENN

VBST

Power-Good

VP

VN

Pull to GND (35

typ)

Pull to GND

(80

typ)





VIN

UVLO

ENP

VBST

ENN

VBST

Power-Good

VP

VN

Pull to GND (35

typ)

Pull to GND

(80

typ)



