ISL98607

4. Application Information

FN8421 Rev.1.00

Page 11 of 29

Jun.3.19

4.1.2 Start and Stop Condition

All I2C communication begins with a Start condition (indicating the beginning of a transaction) and ends with a

Stop condition (signaling the end of the transaction).

A Start condition is signified by a HIGH-to-LOW transition on the serial data line (SDA) while the serial clock line

(SCL) is HIGH. A Stop condition is signified by a LOW-to-HIGH transition on the SDA line while SCL is HIGH. See

the timing specifications in Table 1 on page 10.

The Master always initiates Start and Stop conditions. After a Start condition, the bus is considered “busy.” After a

Stop condition, the bus is considered “free.” The ISL98607 also supports repeated Starts, where the bus remains

busy for the continued transaction(s).

4.1.3 Data Validity

The data on the SDA line must be stable (clearly defined as HIGH or LOW) during the HIGH period of the clock

signal. The state of the SDA line can only change when the SCL line is LOW (except to create a Start or Stop

condition). See the timing specifications in Table 1.

The voltage levels indicating a logical ‘0’ (LOW) and logical ‘1’ (HIGH) are determined by the VIL and VIH

thresholds, respectively, see the “Electrical Specifications” table on page 7.

4.1.4 Byte Format

Every byte transferred on SDA must be 8 bits in length. After every byte of data sent by the transmitter there must

be an Acknowledge bit (from the receiver) to signify that the previous 8 bits were transferred successfully. Data is

always transferred on SDA with the Most Significant Bit (MSB) first. See Acknowledge (ACK).

4.1.5 Acknowledge (ACK)

Each 8-bit data transfer is followed by an Acknowledge (ACK) bit from the receiver. The Acknowledge bit signifies

that the previous 8 bits of data was transferred successfully (master-slave or slave-master).

When the Master sends data to the Slave (such as, during a WRITE transaction), after the 8th bit of a data byte is

transmitted, the Master tri-states the SDA line during the 9th clock. The Slave device acknowledges that it

received all 8 bits by pulling down the SDA line, generating an ACK bit.

When the Master receives data from the Slave (such as during a data READ transaction), after the 8th bit is

transmitted, the Slave tri-states the SDA line during the 9th clock. The Master acknowledges that it received all 8

bits by pulling down the SDA line, generating an ACK bit.

4.1.6 Not Acknowledge (NACK)

A Not Acknowledge (NACK) is generated when the receiver does not pull-down the SDA line during the

acknowledge clock (for example, SDA line remains HIGH during the 9th clock), which indicates to the Master that

it can generate a Stop condition to end the transaction and free the bus.

A NACK can be generated for various reasons, for example:

• After an I2C device address is transmitted, there is NO receiver with that address on the bus to respond.

• The receiver is busy performing an internal operation (such as, reset, recall, etc), and cannot respond.

• The Master (acting as a receiver) needs to indicate the end of a transfer with the Slave (acting as a transmitter).