ISL98607

4. Application Information

FN8421 Rev.1.00

Page 16 of 29

Jun.3.19

4.7

Output Voltage Setting

The VBST, VP, and VN output voltages are adjusted (from the default value) by the VBST_OUT, VP_OUT, and

VN_OUT volatile registers. Equations 1 through 3 on page 14 provide the relation between the value of the I2C

registers and the respective output voltages.

4.8

VP and VN Headroom Voltage and Output Current

The VP and VN headroom voltage is defined as the difference between the VBST output voltage and:

• the maximum VP output voltage: VP headroom

• the absolute value of the VN output voltage: VN headroom

The headroom voltage must be set high enough so that both the VP LDO and VN negative Charge Pump (CP)

can maintain regulation. Primarily, the minimum headroom voltage is a function of the maximum application load

current that the IC needs to support for at least few hundreds of microseconds. Fast output current peaks of only

a few microseconds should not be considered (those instantaneous current peaks are supported by the output

capacitors and not by the regulator).

Note: The headroom voltage should not be set overly high, because increasing headroom generally yields lower

efficiency performance due to increased conduction losses.

For most applications, the ISL98607 default 150mV headroom voltage setting provides optimal performance for

DC output current up to 100mA (maximum). For DC output current between 100mA and 150mA (maximum), the

headroom voltage should be adjusted to 250mV. For example: if a maximum VP to VN load of 150mA is required,

while VP = 5V and VN = -5V, then the minimum boost voltage should be set to VBST = 5.25V.

4.9

Regulator Output Enable/Disable

The boost converter, VBST, will be enabled whenever either ENP or ENN is HIGH, and the VBST enable bit <b0>

in the ENABLE register is set to ‘1’. To disable the boost (and effectively VP and VN), ENN and ENP must be

LOW, or its enable bit set to ‘0’.

The negative charge pump, VN, is enabled whenever ENN is HIGH, and the VN enable bit <b1> in the ENABLE

register is set to ‘1’. To disable, ENN must be LOW, or its enable bit set to ‘0’.

The LDO, VP, is enabled whenever ENP is HIGH, and the VP enable bit <b2> in the ENABLE register is set to ‘1’.

To disable ENP must be LOW, or its enable bit set to ‘0’.

All the ENABLE register bits <b2:b0> are set to ‘1’ by default.

Various options to control the regulator output ON/OFF sequencing are possible with ISL98607, refer to the

“Enable Timing Control Options” on page 19 for more information.

Note, ENP and ENN are logic level inputs with HIGH/LOW thresholds defined by the VIH/VIL specifications,

respectively. These inputs also have 200kΩ (typical) internal pull-down resistance to ground. If the pins are left

hi-impedance, they will default to a LOW logic state. Refer to the “Logic” section of the “Electrical Specifications”

table on page 7 for more information.

4.10 Negative Charge Pump Operation (VN)

The ISL98607 uses a negative charge pump with internal switches to create the VN voltage rail. The charge pump

input voltage VBSTCP comes from the boost regulator output, VBST. The VBST voltage must be greater than the

absolute value of the VN regulation voltage (for example, the headroom voltage has to be > 0V).

Regulation is achieved through a classic voltage mode architecture where an internally compensated gm amplifier

compares the VN output voltage to the internal reference and sets a duty cycle. The duty cycle controls the

amount of time the output capacitor is charged during each switching cycle. The maximum duty cycle is 50%. The

charge pump output capacitor (placed on the VN pin) is charged and discharged through internal 450mA current

sources to minimize system noise.