ISL98607

4. Application Information

FN8421 Rev.1.00

Page 10 of 29

Jun.3.19

4.

Application Information

4.1

I2C Digital Interface

The ISL98607 uses a standard I2C interface bus for communication. The two-wire interface links a Master(s) and

uniquely addressable Slave devices. The Master generates clock signals and is responsible for initiating data

transfers. The serial clock is on the SCL line and the serial data (bi-directional) is on the SDA line. The ISL98607

supports clock rates up to 400kHz (Fast-Mode), and is backwards compatible with standard 100kHz clock rates

(Standard-mode).

The SDA and SCL lines must be HIGH when the bus is free (not in use). An external pull-up resistor (typically

2.2kΩ to 4.7kΩ) or current-source is required for SDA and SCL.

The ISL98607 meets standard I2C timing specifications. Figure 13 and Table 1 on page 10 show the standard

timing definitions and specifications for I2C communication.

4.1.1 Low-Power Mode

The I2C interface of ISL98607 remains active even when both ENN and ENP are LOW for up to 30ms. When ENN

and ENP both remain LOW, and no I2C communication occurs for more than 30ms, the ISL98607 enters a

low-power mode. This mode disables the I2C interface, but the interface is re-activated as soon as ISL98607

detects a logic LOW on SCL or SDA.

For the ISL98607, when the I2C interface is not used, both the SDA and SCL inputs must be tied HIGH (such as

to VIN) or pulled-up to a logic HIGH level, to ensure the part enters the Low-Power consumption mode when ENN

and ENP are held LOW longer than 30ms. This feature optimizes battery power saving in handheld products,

such as, when the display system is put into a standby/sleep mode.

Figure 13. I2C Timing Definitions

Table 1.

I2C Timing Characteristics

Parameter

Symbol

Fast-Mode

Standard-Mode

Unit

Min

Max

Min

Max

SCL Clock Frequency

fSCL

0

400

0

100

kHz

Set-Up Time for a Start Condition

tSU:STA

0.6

-

4.7

-

µs

Hold Time for a Start Condition

tHD:STA

0.6

-

4.0

-

µs

Set-Up Time for a Stop Condition

tSU:STO

0.6

-

4.0

-

µs

Bus Free Time between a Stop and Start Condition

tBUF

1.3

-

4.7

-

µs

Data Set-up Time

tSU:DAT

100

-

250

-

ns

Data Hold Time

tHD:DAT

0-

0

-

µs

Rise Time of SDA and SCL (Note 10)tr

20 + 0.1Cb

300

-

1000

ns

Fall Time of SDA and SCL (Note 10)tf

20 + 0.1Cb

300

-

300

ns

Capacitive Load on Each Bus Line (SDA/SCL)

Cb

-

400

-

400

pF

Note:

10. Cb = total capacitance of one bus line in pF.

tSU:STA

Start

tHD:STA

tr

tf

tSU:DAT

tHD:DAT

Stop

Start

tBUF

tSU:STO

VIH

VIL

VIH

VIL

SDA

SCL

tr

tf