ISL98607

4. Application Information

FN8421 Rev.1.00

Page 17 of 29

Jun.3.19

4.11 PFM

The ISL98607 features light-load Pulse Frequency Modulation (PFM) mode for both the boost regulator and

charge pump to maximize efficiency at light loads.

The ISL98607 always uses PWM mode at heavy loading, but when PFM mode is enabled using the respective

PFM mode enable/disable register bit, it automatically switches to PFM mode at light loads to optimize efficiency.

There is hysteresis built-in with the PFM transition for when the transition is from light to heavy or heavy to light

loading, which prevents inadvertently going back and forth between PWM and PFM modes.

4.12 Fault Protection and Monitoring

The ISL98607 features extensive protections to automatically handle failure conditions and protect the IC and

application from damage.

4.12.1 Overcurrent Protection (OCP)

The overcurrent protection limits the VBST nMOSFET current on a cycle-by-cycle basis. When the nMOSFET

current reaches the current limit threshold, the nMOSFET is turned off for the remainder of that cycle. Overcurrent

protection does not disable any of the regulators. When the fault is removed, the IC continues with normal

operation.

4.12.2 Undervoltage Lockout (UVLO)

If the input voltage (VIN) falls below the VUVLO_HYS level of ~2.3V (typical), the VBST, VP, and VN regulators are

disabled. All the rails restart with normal soft-start operation when the VIN input voltage is applied again (rising

VIN > VUVLO). See the “Electrical Specifications” table on page 6 for the UVLO specifications.

Note: The I2C registers (logic) are not cleared/reset to default by the falling VIN UVLO. The logic states are

retained if VIN remains above 2V (typical). When VIN falls below 2V, all logic is reset. VIN should fall below 2V

(ideally to GND) before power is reapplied to ensures a full power cycle/reset of the device.

4.12.3 Over-Temperature Protection (OTP)

The ISL98607 has a hysteretic over-temperature protection threshold set at +130°C (typical). If this threshold is

reached, the VBST, VP, and VN regulators are disabled immediately. As soon as temperature falls by 10°C

(typical) then all the regulators automatically restart.

All register bits, except for bit <b0> of the FAULT register (Register Address 0x04), remain unaffected during an

OTP fault event. When an OTP event occurs, FAULT register bit <b0> is latched to ‘1’. This bit is reset/cleared by

cycling both ENN and ENP (set LOW, then HIGH) at the same time, or by cycling VIN power. Bit <b0> can also be

reset after it is read twice by I2C. A single I2C read returns the bit value (status), and a second read resets only the

OTP bit.

Output undervoltage protection is disabled during an OTP event. The output voltages decrease during an OTP

event because the regulators are disabled, which does not trigger a UVP fault.

4.12.4 Undervoltage Protection (UVP)

The ISL98607 includes output undervoltage protection. Undervoltage protection disables the regulator whenever

the output voltage of VBST or VP falls below 60% of its set/regulated voltage, or the output voltage of VN goes

above 60% of its set/regulated voltage, for 100µs or more. If the output voltage exceeds the 60% condition for

less than 100µs, no fault occurs.

Depending on which regulator(s) fault, bit(s) <b3>, <b2>, or <b1> in the FAULT register are latched to ‘1’ for VP,

VN, and VBST faults, respectively. The bit(s) are reset/cleared by cycling both ENN and ENP (set LOW, then

HIGH) at the same time, or by cycling VIN power.