HC705CT4GRSSLASHD datasheet(101/152 Pages) NXP

101 / 152 page

Comparators

Comparator Control/Status Register

MC68HC705CT4 — Rev. 2.0

General Release Specification

MOTOROLA

Comparators

101

13.3 Comparator Control/Status Register

CMP3 — Comparator 3 Output

This bit is implemented in two ways: as a real-time comparator output

or as a latched interrupt source. The state of CM3IE determines which

implementation is selected.

CM3IE = 0 (nonlatched mode) — This status bit is is cleared only by

two means:

1. Clearing CM3IE while the voltage at CMP3+ is less than CMP3–

2. By an external reset

CM3IE = 1 (latched mode) — This latched status bit is set when the

voltage at CMP3+ (PD0) is larger than that of CMP3– (internal voltage

reference ~ 2 VDD/3). An interrupt is then initiated ($1FFA–$1FFB).

CMP2 — Comparator 2 Output

This status bit is set when the voltage at CMP12+ is larger than that

of CMP2–, otherwise, it is cleared. Reset clears this bit because the

comparator is disabled.

CMP1 — Comparator 1 Output

This status bit is set when the voltage at CMP12+ is larger than that

of CMP1–, otherwise, it is cleared. Reset clears this bit because the

comparator is disabled.

Address:

$0022

Bit 7

654321

Bit 0

Read:

CMP3

CMP2

CMP1

CM3IE

CEN3

CEN2

CEN1

Write:

Reset:

00000000

= Unimplemented

Figure 13-2. Comparator Control/Status Register (CMPCSR)

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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