HC705CT4GRSSLASHD datasheet(36/152 Pages) NXP

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Interrupts

General Release Specification

MC68HC705CT4 — Rev. 2.0

Interrupts

MOTOROLA

4.3 CPU Interrupt Processing

Interrupts cause the processor to save register contents on the stack

and to set the interrupt mask (I bit) to prevent additional interrupts. Unlike

RESET, hardware interrupts do not cause the current instruction

execution to be halted, but are considered pending until the current

instruction is complete.

If interrupts are not masked (I bit in the CCR is clear) and the

corresponding interrupt enable bit is set, the processor will proceed with

interrupt processing. Otherwise, the next instruction is fetched and

executed. If an interrupt occurs, the processor completes the current

instruction, stacks the current CPU register states, sets the I bit to inhibit

further interrupts, and finally checks the pending hardware interrupts. If

more than one interrupt is pending after the stacking operation, the

interrupt with the highest vector location shown in Table 4-1 will be

serviced first. The SWI is executed the same as any other instruction,

regardless of the I-bit state.

When an interrupt is to be processed, the CPU fetches the address of

the appropriate interrupt software service routine from the vector table at

locations $1FF4–$1FFF as defined in Table 4-1.

Table 4-1. Vector Address for Interrupts and Reset

Flag

Name

Interrupt

CPU

Interrupt

Vector

Address

N/A

Reset

RESET

$1FFE–$1FFF

N/A

Software

SWI

$1FFC–$1FFD

CMCSR

CMP3

CMP3, External Interrupts*

CMP3/IRQ

$1FFA–$1FFB

TSR

OCF, ICF, TOF

16-bit Timer Interrupts

TIMER

$1FF8–$1FF9

SSSR

SSIF

SSI Interrupt

SSI

$1FF6–$1FF7

CTCSR

TOFE, RTIE

Core Timer Interrupts

TIMER, RTI

$1FF4–$1FF5

* External interrupts include IRQ and PORTC sources.

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

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