HC705CT4GRSSLASHD datasheet(86/152 Pages) NXP

номер детали	HC705CT4GRS/D

подробное описание детали	General Release Specification

PDF	152 Pages

Scroll/Zoom	100%

производитель	NXP [NXP Semiconductors]

домашняя страница	http://www.nxp.com

Logo

86 / 152 page

Dual Phase-Locked Loop (PLL)

General Release Specification

MC68HC705CT4 — Rev. 2.0

Dual Phase-Locked Loop (PLL)

MOTOROLA

11.2 Introduction

This dual PLL is similar to that of the MC145162 60-MHz universal

programmable dual PLL frequency synthesizer. It is especially designed

for CT-1 cordless phone applications.

The PLL features fully programmable 16-bit receive, 16-bit transmit, and

12-bit reference ripple down counters. It also has two independent

phase detectors for transmit and receive loops.

The FinTx and FinRx signals are input to the PLL transmit and receive

counters, respectively. They are typically driven by the loop VCO and

AC-coupled. The minimum input signal level is 200 mVp-p @ 60.0 MHz.

Figure 11-1. Dual PLL Block Diagram

OSC

12-BIT PROGRAMMABLE

REFERENCE COUNTER

÷ 4

÷ 5

TxPDOUT

RxPDOUT

16-BIT PROGRAMMABLE

TX COUNTER

16-BIT PROGRAMMABLE

RX COUNTER

FinT

FinR

PLS1

PLS0

MCU BUS

(10.24 MHz)

÷ 25

PHASE

DETECTOR

PHASE

DETECTOR

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

HC705CT4GRS/D датащи(PDF) 86 Page - NXP Semiconductors

HC705CT4GRS/D датащи(HTML) 86 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL