DA6021 datasheet(8/225 Pages) RENESAS

8 / 225 page

DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

8 of 224

www.dialog-semiconductor.com

Figures

Figure 1: Overview Diagram ....................................................................................................................... 17

Figure 2: Detailed Block Diagram ............................................................................................................... 18

Figure 3: Maximum Allowed Peak Power ................................................................................................... 20

Figure 4: DA6021 Power States ................................................................................................................. 30

Figure 5: VSYS Areas................................................................................................................................. 31

Figure 6: SoC Power States ....................................................................................................................... 32

Figure 7: Address Range and Pages ......................................................................................................... 37

Figure 8: State Transitions.......................................................................................................................... 38

Figure 9: Cold Boot Power Sequencing Diagram, Valid Battery Insertion ................................................. 43

Figure 10: Enter S0iX Sequencing Diagram (VCCAPWROKCFG=1)........................................................ 47

Figure 11: Enter S0iX Sequencing Diagram (VCCAPWROKCFG=0)........................................................ 48

Figure 12: Exit S0iX Sequencing Diagram (VCCAPWROKCFG=1) .......................................................... 50

Figure 13: Exit S0iX Sequencing Diagram (VCCAPWROKCFG=0) .......................................................... 51

Figure 14: Enter S3 Sequencing Diagram .................................................................................................. 53

Figure 15: Exit S3 Sequencing Diagram .................................................................................................... 54

Figure 16: Enter S4 Sequencing Diagram .................................................................................................. 55

Figure 17: Exit S4 Sequencing Diagram .................................................................................................... 56

Figure 18: Cold Off Power Sequencing Diagram (SUSPWRDNACKCFG=1) ........................................... 58

Figure 19: Power Button forced Cold Off.................................................................................................... 62

Figure 20: Catastrophic Event (except VSYSOVP) Shutdown Sequence ................................................. 63

Figure 21: VSYSOVP Shutdown Sequence ............................................................................................... 63

Figure 22: Modem Reset Sequencing Diagram ......................................................................................... 64

Figure 23: Definition of VHYS..................................................................................................................... 70

Figure 24: Measurement Points for VCLK.................................................................................................. 71

Figure 25: SoC Driving Timing Definition ................................................................................................... 72

Figure 26: DA6021 Driving Timing Definition ............................................................................................. 72

Figure 27: VCC Block Diagram .................................................................................................................. 79

Figure 28: VCC Timings ............................................................................................................................. 80

Figure 29: VCC Efficiency........................................................................................................................... 81

Figure 30: Buck VNN Block Diagram ......................................................................................................... 82

Figure 31: VNN Efficiency........................................................................................................................... 83

Figure 32: V1P0A Power Rail Block Diagram ............................................................................................ 84

Figure 33: V1P0A Efficiency ....................................................................................................................... 86

Figure 34: Buck V1P05S Block Diagram.................................................................................................... 89

Figure 35: V1P05S Efficiency ..................................................................................................................... 91

Figure 36: Buck V1P8A Power Rail Block Diagram ................................................................................... 92

Figure 37: V1P8A Efficiency ....................................................................................................................... 93

Figure 38: VDDQ Power Domain Block Diagram ....................................................................................... 98

Figure 39: VDDQ Efficiency...................................................................................................................... 100

Figure 40: Buck Boost V2P85S Power Domain Block Diagram............................................................... 105

Figure 41: V2P85S Efficiency................................................................................................................... 107

Figure 42:V3P3A Power Domain Block Diagram ..................................................................................... 109

Figure 43:V3P3A Efficiency ...................................................................................................................... 110

Figure 44:V5P0S Power Domain Block Diagram ..................................................................................... 113

Figure 45:V5P0S Efficiency ...................................................................................................................... 114

Figure 46: Current Measurement Tolerance Boundary ............................................................................ 118

Figure 47: VCC/VNN ADC Current Coding .............................................................................................. 119

Figure 48: Typical VCC Current Sensing Error ........................................................................................ 119

Figure 49: Typical VNN Current Sensing Error ........................................................................................ 119

Figure 50: V1P0A ADC Current Coding ................................................................................................... 120

Figure 51: Typical V1P0A Current Sensing Error..................................................................................... 120

Figure 52: V1P05S ADC Current Coding ................................................................................................. 121

Figure 53: Typical V1P05S Current Sensing Error................................................................................... 121

Figure 54: VDDQ ADC Current Coding .................................................................................................... 122

Figure 55: Typical VDDQ Current Sensing Error ..................................................................................... 122

Figure 56: I2C Fast Speed Write .............................................................................................................. 123

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