DA6021 datasheet(36/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

36 of 224

www.dialog-semiconductor.com

Notes:

don’t care

RSMRST_B=1 for any sleep signal assertion to be valid

The normal (except catastrophic or critical events) power state transition sequence is: SOC G3->SOC

S4->SOC S3->SOC S0IX->SOC S0 based on the conditions or in reverse order. Power state transition

is from one state to the next state based on sleep signals from the SOC without skipping states. For

example, if the PMIC is currently in SOC S0 state, sleep signals SLP_S0IX, SLP_S3_B, SLP_S4_B are

all asserted. The PMIC will not jump directly to SOC S4 without first going to SOC S0IX then to SOC S3.

4. To exit from SOC S3 and SOC S4, BATLOW_B=1.

5. Normally SLP_S0IX_B =0, SLP_S3_B=0 when SLP_S4_B=0.

6. Normally SLP_S0IX_B =0 when SLP_S3_B=0. SUSPWRDNACK=1 in this power state.

7. Normally SUSPWRDNACK=1 in this power state.

DA6021 Power State Transitions and Sleep Signals

9.3.6

The table below summarizes how DA6021 transitions from one power state to the next based on sleep signals

and SUCPWRDNACK.

SUSPWDNA

SUSPWRDN

ACKCFG

SLP_S4_B

SLP_S3_B

SLP_S0iX_B

Present

State

Next State

SOC_S4

SOC_G3

SOC_S4

SOC_S3

SOC_S4

SOC_S3

SOC_S0iX

SOC_S0

SOC_S0iX

SOC_S3

SOC_S0

SOC_S0iX

Table 13: DA6021 State Transition and Sleep Signals

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