DA6021 datasheet(41/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

41 of 224

www.dialog-semiconductor.com



S rails

: V5P0S, VNN, V1P05S, V1P0S, V1P8S, V1P2S, V3P3S and V2P85S. They remain on in “SOC

0IX” state. They are turned off in “SOC S3” state.



SX rails

: VDDQ_VTT, V1P0SX and V1P2SX. They are on in “SOC S0” state. They are turned off in

“SOC S0IX” state.



Default On rails: VRs that are powered on during COLD BOOT by the power sequencing state

machine.



Defaults Off rails: VRs that are not powered on during COLD BOOT by the power sequencing state

machine. They are managed by the SOC. Their on/off status depends on a platform device or other

conditions.

Cold Boot

10.3.1

A cold boot sequence is followed whenever DA6021 is fully turning on the system from a powered-down state.

As such, a cold boot sequence begins at the “SOC G3” state, and terminates at the “SOC S0” state. Once all of

the rails are on, the COREPWROK signal will assert and the PLTRST_B will de-assert. This will effectively turn

on the SOC in order for it to begin executing code and controlling the system.

During this state transition, one or more of the sleep signals (SLP_S*_B) could be asserted at some point of

time. The VRs, LDOs, internal and external switches are turned on in the requested power sequence order into

normal operational.

Furthermore, the rails are turned on one at a time in a ramp-rate controlled manner (voltage slew rate limited) in

order to avoid battery inrush current situations that could cause shut down events.

All the triggers listed in the table below will cause DA6021 bringing up the SUS rails. After that, signals from the

SOC (SLP_S4_B, SLP_S3_B) are needed for DA6021 completing the cold boot sequence. Battery insertion is

used as an illustration of Cold Boot power sequence due to one of triggers.

Event

Conditions (all mandatory)

USB VBUS Inserted

(SVBUSDET)

 USBWAKEEN is set

 VSYS valid (after VBUS debounce satisfied)

 VBUS valid (after VBUS debounce satisfied)

 VBAT valid (SBATDET=1 and BATLOW_B=1)

AC/DC Adapter

Inserted

(SVDCINDET)

 ADPWAKEEN is set

 VSYS valid (after adapter debounce satisfied)

 VDCIN valid (after adapter debounce satisfied)

 VBAT valid (SBATDET=1 and BATLOW_B=1 if BATRMPDEN set, or BATLOW_B=1

if BATRMPDEN cleared).

Main Battery

Inserted

(SBATDET:01)

 BATWAKEEN is set

 VSYS valid (after battery detection debounce)

 VBAT valid (after battery detection debounce, BATLOW_B=1)

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