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DA6021 датащи(PDF) 40 Page - Renesas Technology Corp

номер детали DA6021
подробное описание детали  HIGHLY INTEGRATED POWER MANAGEMENT IC FOR INTEL® ATOM™ Z3000 PROCESSOR
PDF  225 Pages
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производитель  RENESAS [Renesas Technology Corp]
домашняя страница  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

DA6021 датащи(HTML) 40 Page - Renesas Technology Corp

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DA6021
HIGHLY INTEGRATED POWER MANAGEMENT IC FOR
INTEL® ATOM™ Z3000 PROCESSOR
Company Confidential
Data Sheet
Version 3.A - Final
31-Jan-14
© 2014 Dialog Semiconductor GmbH
40 of 224
www.dialog-semiconductor.com
DA6021 Power Sequences
10.3
There are 10 power state transitions to be performed in DA6021. These are:
Cold Boot
: A cold boot sequence begins at the “SOC G3” state, and terminates at the “SOC S0” state.
Once all of the rails are on, the COREPWROK signal will assert and the PLTRST_B will de-assert. This
will effectively turn on the SOC in order for it to begin executing code and controlling the system.
Warm Reset: A Warm Reset resets the SOC as well as the I2C and SVID interfaces (reset
corresponding state machine, ignore any on-going transaction on the bus) in the PMIC. In addition the
VCC, VNN will change the output voltage to the VBOOT settings. PMIC configuration registers are not
reset to default. During a Warm Reset, only the PLTRST_B pin to the SOC is toggled. All rails remain in
regulation. Warm reset can only be issued while the SoC stays in SOC_S0 state.
Enter SOC S0iX: The S0IX state is entered when the SOC is in a shallow sleep state. This state is
entered when the SOC asserts the SLP_S0IX_B (LOW) pin to the PMIC. VDDQ_VTT and SX rails are
turned off. The VCC rail is turned off by SVID commands (not by SLP_S0IX_B signal). The rest of the
VRs remain on but enter into power save mode.
Exit SOCS0iX: The S0IX state is exited when the SOC de-asserts the SLP_S0IX_B pin (HIGH).
VDDQ_VTT and SX rails are turned on. The VCC rail will be turned on by SVID commands (not by
SLP_S0IX). The rest of the rails will come out of power save mode. Exiting the SOC_SX state will be
performed within maximum 200µs.
Enter SOC_S3: The S3 state is entered when the SOC asserts the SLP_S3_B pin (LOW). VRs that
remain on enter into power save mode.
Exit SOC_S3: The S3 state is exited when the SOC de-asserts the SLP_S3_B pin (HIGH). Voltage rails
will be turned on and come out of power save mode. Exiting SOC_S3 state will be performed within 2ms
maximum.
Enter SOC_S4: The S4 state is entered when the SOC asserts the SLP_S4_B pin (LOW). VRs that
remain on enter into power save mode.
Exit SOC_S4: The S4 state is exited when the SOC de-asserts the SLP_S4_B pin (HIGH). Voltage rails
will be turned on and come out of power save mode.
Cold OFF: PMIC will go into SOC_G3 and stay until a wakeup event is not bringing it back to active
state.
Modem Reset: A Modem Reset task is initiated by setting the MODEMRSTSEQ bit in the MODEMCTRL
register. (The MODEMOFF bit in the same register directly controls the status of the MODEM_OFF_B
output pin, but does not launch this task). The Modem Reset task toggles the SDWN and
MODEM_OFF_B pins, implementing appropriate (modem-specific) delay timings.
Several of these state transitions are triggered by hardware events, such as a power button event, or power
source insertion. The transitions are gated by SOC signals such as, SLP_S0IX, SLP_S3_B, SLP_S4_B and
SUSPWRDNACK.
The behaviours
associated with each of these state transitions are stored in the PMIC’s power sequencing state
machine.
The sections below describe the trigger sources of each transition and the default sequencing behaviour.
The voltage rails are classified in the following categories which will be referred to in such a way to simplify the
power state transition (power sequencing) diagrams:
SUS rails (A rails): V1P0A, V1P8A, V1P2A and V3P3A. They together with VUSBPHY remain on in
“SOC S4” state. They are turned off in “SOC G3” state.
U rails: V1P8U, together with VDDQ, VREFDQ0/1
remains on in “SOC S3” state. They are turned off in
“SOC S4” state.



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