DA6021 datasheet(3/225 Pages) RENESAS

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DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

3 of 224

www.dialog-semiconductor.com

SDMMC3_PWR_EN_B.................................................................................................. 28

9.1.29

MODEM_OFF_B............................................................................................................ 28

9.1.30

SDWN_B........................................................................................................................ 28

9.1.31

USBRST_B .................................................................................................................... 28

9.1.32

GPIOs ............................................................................................................................ 28

9.1.33

Burst Control Unit........................................................................................................... 29

9.1.34

PWM[2:0] ....................................................................................................................... 29

9.1.35

DISPLAY ........................................................................................................................ 29

9.1.36

ADC................................................................................................................................ 29

9.1.37

DA6021 Power States ................................................................................................................ 30

9.2

SoC Power States ...................................................................................................................... 32

9.3

SOC_S0 State ............................................................................................................... 32

9.3.1

SOC S0iX State ............................................................................................................. 33

9.3.2

SOC S3 State................................................................................................................. 34

9.3.3

SOC S4 State................................................................................................................. 35

9.3.4

Truth Table of Sleep Signals and DA6021 Final Power States ..................................... 35

9.3.5

DA6021 Power State Transitions and Sleep Signals .................................................... 36

9.3.6

Register File and Address Range .............................................................................................. 37

9.4

Slave ID versus DA6021 Pages .................................................................................... 37

9.4.1

10. Power Controller State Machine ....................................................................................................... 38

Overview .................................................................................................................................... 38

10.1

Power State Transitions ............................................................................................................. 38

10.2

Sequencing .................................................................................................................... 39

10.2.1

DA6021 Power Sequences ........................................................................................................ 40

10.3

Cold Boot ....................................................................................................................... 41

10.3.1

Warm Reset Sequence .................................................................................................. 46

10.3.2

Enter SOC S0iX Mode ................................................................................................... 46

10.3.3

Exit SOC S0iX Mode...................................................................................................... 49

10.3.4

Enter SOC S3 Mode ...................................................................................................... 52

10.3.5

Exit SOC S3 Mode ......................................................................................................... 54

10.3.6

Enter SOC S4 Mode ...................................................................................................... 55

10.3.7

Exit SOC S4 Mode ......................................................................................................... 56

10.3.8

Cold Off .......................................................................................................................... 57

10.3.9

Modem Reset Sequence ............................................................................................... 64

10.3.10

PMIC Resets .............................................................................................................................. 65

10.4

Wake Events .............................................................................................................................. 65

10.5

11. Platform Power Domains ................................................................................................................... 66

Power Domains Summary ......................................................................................................... 66

11.1

Voltage Rail ON/OFF On Various Power States........................................................................ 68

11.2

PMIC Current Consumption in Various States........................................................................... 68

11.3

Voltage Rail Control Mechanism ................................................................................................ 69

11.4

SVID Interface ............................................................................................................................ 69

11.5

SVID DC Electrical Parameters ..................................................................................... 69

11.5.1

VCLK Timing Parameters .............................................................................................. 70

11.5.2

Data Sampling and Timing............................................................................................. 71

11.5.3

SVID Command Set....................................................................................................... 73

11.5.4

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