DA6021 datasheet(39/225 Pages) RENESAS

39 / 225 page

DA6021

HIGHLY INTEGRATED POWER MANAGEMENT IC FOR

INTEL® ATOM™ Z3000 PROCESSOR

Company Confidential

Data Sheet

Version 3.A - Final

31-Jan-14

39 of 224

www.dialog-semiconductor.com

The figure above represents DA6021 power state transitions. There are several events and condition for these

transitions to occur. Following is the list of conditions used in the figure.



PH_EVENT: this is a catastrophic event. At any time the system does an immediate shutdown 90µs

after the shutdown warning and goes directly to the SOC_G3 state.



CT_EVENT: these are all critical events. DA6021 will shut down via power down sequencing which is

driven from the PMIC, regardless of the SoC handshake.



U2S*: Indicates a move to the next SOC_S* state. The direction is upwards. The reason can be that one

of the SLP_S*_B signals have changed or PWRBTN has been pressed.



D2S*: Indicates a move to the next SOC_S* state. The direction I downwards. Reason can be a change

on one of the SLP_S*_B signals.



D2G3: Can be asserted if DA6021 is sensitive to SUSPWRDNACK input and SUSPWRDNACK = 1.



SYS_WAKEUP: represents a valid wakeup event from system power down. This event is generated

from the sysco block.



UV_EVENT: represents an under voltage event in DA6021. Under voltage event belongs to the critical

event but the final state will be G3, instead of SOC_G3.



VSYS_VALID: this means that VSYS has crossed the 3.0V and can proceed to SOC_G3 and wait for

boot condition

Refer to the table below for U2 and D2 specific conditions.

Condition

NX_ST

Events

SLP_S4_B

SLP_S3_B

SLP_SX_B

U2S3

U2SX

U2S0

D2SX

D2S3

D2S4

SOC_S4

SOC_S3

SOC_S4

SOC_S3

SOC_SX

SOC_S0

SOC_SX

SOC_S3

SOC_SX

SOC_S3

SOC_S0

SOC_SX

SOC_S0

SOC_SX

SOC_S0

SOC_SX

Table 15:U2 & D2 Event Generation Table

A soft reset can be generated in application and via configuration in SOC_SX and SOC_S0 states. In other

modes it can be generated even in other states where the I2C slave is available.

Sequencing

10.2.1

Each PMIC component (such as a

DC/DC converter, LDO, internal or external power switch … ) can be placed

with high flexibility into the power sequence, whereas enabling and disabling such a component during power-up

and power-down can be programmed independently.

The sequencing is defined by Intel processor specification, implemented and evaluated accordingly. Customers

requesting power sequencing other than specified, please contact Dialog Semiconductor.

DA6021 датащи(PDF) 39 Page - Renesas Technology Corp

DA6021 датащи(HTML) 39 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL