© 2002 QuickLogic Corporation
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Preliminary
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www.quicklogic.com
Device Highlights
LVDS SERDES Basic Features
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10 High Speed Bus LVDS Serial Links—
bandwidth up to 5 Gbps
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Eight Independent Bus LVDS serial
transceivers with operating speeds to 632
Mbps per channel
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Two Independent Bus LVDS clock serial
transceivers with operating speeds to
400 MHz per channel
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Integrated clock and data recovery (CDR)
with no external analog components
required
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CDR bypass for applications with external
clock source
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Programmable serial to parallel
configuration
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10-bit data width—with
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clock recovery
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4-bit, 7-bit and 8-bit data widths—
with external clock
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1-bit asynchronous level conversion
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Fast Lock and Random (auto) Lock capable
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Lock signal feedback
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I/O support for LVTTL, LVCMOS, PCI,
GTL+, SSTL2, SSTL3, LVDS, LVPECL
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Low Power/Independent power-down
mode for each SERDES channel
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IEEE1149.1 JTAG Support &
boundary scan
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Operation over PCB or backplane traces, or
across twisted pair cabling up to 25 m
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Point-to-Point, Multi-Point, and Multi-Drop
Support
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Pre-Emphasis Control on each LVDS
Channel Link
Extended Features
The following can be implemented into the
programmable logic:
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UTOPIA Level 2, 16-bit wide System
interface (up to 50 MHz) with parity support
for ATM applications
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UTOPIA Level 3 compatible 8-bit wide
system Interface (up to 100 MHz) with parity
support for ATM applications
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CSIX-L1 32-bit switch fabric interface (up to
100 MHz)
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Supports Generic 8,16,32-bit
microprocessor bus interface for
configuration, control and status monitoring
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Supports Generic 32, 64-bit peripheral bus
interface for bridging functions
Flexible Programmable Logic
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2,016 Programmable Logic Cells
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536 K System Gates
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Muxed architecture; non-volatile technology
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Completely customizable for any digital
application
Dual Port SRAM Blocks
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36 Dual Port SRAM Blocks
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Configurable array sizes (by 2, 4, 9, 18)
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< 3 ns access times, FIFO capable of over
300 MHz
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Configurable as RAM or FIFO
QL82SD Device Data Sheet
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