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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
21
www.quicklogic.com
Electrical Specification - Programmable Fabric
DC Characteristics
DC Input/Output Levels
NOTE: The above table gives the programmable logic timing model for the QuickSD device.
The programmable logic includes the following major elements: Super Logic (Flip-Flop and
Combinational Circuit), Clock, and I/O.
Table 19: DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Units
II
I or I/O Input Leakage Current
VI = VCCIO or GND
-10
10
µA
IOZ
3-State Output Leakage Current
VI = VCCIO or GND
-10
10
µA
CI
Input Capacitance a
a. Capacitance is sample tested only. Clock pins are 12 pF maximum.
8pF
IOS
Output Short Circuit Current b
b. Only one output at a time. Duration should not exceed 30 seconds.
Vo = GND
-15
-180
mA
Vo = VCC
40
210
mA
ICC
D.C. Supply Current c
c. For -4/-5/-6/-7 commercial grade devices only. Maximum ICC is 3 mA for all industrial grade devices.
VI,Vo =VCCIO or GND 0.50 (typ)
2
mA
ICCIO
D.C. Supply Current on VCCIO
02
mA
IREF
D.C. Supply Current on VREF
-10
10
µA
IPD
Pad Pull-down (programmable)
VCCIO = 3.6 V
150
µA
Table 20: DC Input/Output Levels
VREF
VIL
VIH
VOL
VOH
IOL
IOH
VMIN
VMAX
VMIN
VMAX
VMIN
VMAX
VMAX
VMIN
mA
mA
LVTTL
n/a
n/a
-0.3
0.8
2.0
VCCIO - 0.3
0.40
2.40
2.0
-2.0
LVCMOS2
n/a
n/a
-0.3
0.7
1.7
VCCIO - 0.3
0.70
1.70
2.0
-2.0
GTL+
0.88
1.12
-0.3 V
REF - 2.0
VREF + 2.0 VCCIO - 0.3
0.60
n/a
40
n/a
PCI
n/a
n/a
-0.3 0.30 × V
CC
0.50
× V
CC
VCCIO - 0.5 0.10 × VCC 0.90 × VCC 1.5
-0.5
SSTL2
1.15
1.35
-0.3 V
REF - 0.18
VREF + 0.18 VCCIO + 0.3
0.74
1.76
7.6
-7.6
SSTL3
1.30
1.70
-0.3 V
REF - 0.20
VREF + 2.0 VCCIO + 0.3
1.10
1.90
8.0
-8.0
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