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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
27
www.quicklogic.com
Table 26: Output Register Cell
Figure 39: Output Register Cell Timing
Electrical Specification - RAM Block
Figure 40: RAM Module
Symbol
Parameter
Propagation delay (ns)
Output Register Cell Only
tOUTLH
Output Delay low to high (10% of H)
0.40
tOUTHL
Output Delay high to low (90% of H)
0.55
tPZH
Output Delay tri-state to high (10% of Z)
2.94
tPZL
Output Delay tri-state to low (90% of Z)
2.34
tPHZ
Output Delay high to tri-State
3.07
tPLZ
Output Delay low to tri-State
2.53
tCO
Clock to out delay
3.15 (fast slew) 10.2(slow slew)
L
H
L
H
tOUTLH
tOUTHL
L
H
Z
tPZH
L
H
Z
tPZL
L
H
Z
tPLZ
L
H
Z
tPHZ
WA
WD
WE
WCLK
RE
RCLK
RA
RD
[9:0]
[17:0]
[9:0]
[17:0]
MODE
ASYNCRD
[1:0]
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