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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
49
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LVDS SERDES Internal Signals (Channel Clocks A and B)
NOTE: All ClkA signals above repeat for ClkB. SERDES channel clocks A and B are
identical.
208 PQFP Pinout Diagram
Figure 56: QL82SD - 208PQFP Pinout Diagram
Table 41: LVDS SERDES Internal Signals (Channel Clocks A and B)
Signal Name
Description
ClkA_rst
Channel Clock A Reset Signal
ClkA_oe
Channel Clock A Output Enable (1 =transmit, 0=receive)
ClkA_en
Channel Clock A Enable (reduces power when set to 0)
ClkA_mode[1:0]
Channel Clock A MODE pins. See the SERDES Channel Clock Functional
Description
ClkA_txclk
Channel Clock A Parallel Transmit Clock
ClkA_rxclk
Channel Clock A Parallel Receive Clock
QuickSD
QL82SD-6PQ208C
Pin #1
Pin #53
Pin #105
Pin #157
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