20 / 60 page
www.quicklogic.com
© 2002 QuickLogic Corporation
•
•
•
•
•
•
QL82SD Device Data Sheet Rev C
Preliminary
20
Figure 26: Channel Link Mode Deserializer Receive (Using 8:1 Mode as Example)
Figure 27: 1:1 Mode Asynchronous Level Conversion Mode Deserializer Delays
SERDES Bit Error Rate
The following table indicates the SERDES bit error rate at TA = 25
° C and
PLLVcc = 2.5 V unless otherwise specified.
Table 18: Serializer/Deserializer Bit Error Rate
Modes
Bit Error Rate
10:1
< 1 x 10-12
8:1
< 1 x 10-12
7:1
< 1 x 10-12
4:1
< 1 x 10-12
[bit3] [bit2] [bit1] [bit0] [bit7] [bit6] [bit5] [bit4]
Pad_Clkx_p/n
Pad_Chx_p/n
SerialClock
(Internal)
RXD [1] max
[0] max
[1] min
[0] min
Chx
_rxclk
Chx_rxd[7:0]
Note:
[N-1] denotes
physical strobe positions
wrt Pad_ClkX_p/n while
Pad_ChX_p/n bit[n] refers
logical bit positions
wrt ChX
_rxd [7:0].
t
t
t
RXD
t
RXD
t
RXD
t
t
t
t
RCP
SCP
SCD
Strobe
RXDS
RXDH
t
t
RXPD
DD
RXD
t
to
Ch0_txd [0]
Pad_Ch0_p/n
ClkA_txclk
Pad_ClkA_p/n
t
ASD
t
ASC
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
