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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
19
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Figure 23: 10:1 Mode Deserializer Receive with Embedded Clock
Figure 24: Deserializer PLL Lock Time from Power Down
Figure 25: 10:1 Mode Deserializer PLL Lock Time from SYNCPAT
RXPD
DD
t
A
B
Ch0_txclk
Ch0_rxd[9:0]
Ch0_rxclk
pad_Ch0_p/n
t
2.0V
Enable
Chx_txclk
Pad_Chx_p/n
Chx_lock
Chx-rxd
[N-1,0]
Chx_rxclk
OE
t ZHLK
DSR1
t
SYNC patterns
ZHR or
ZLR
t
t
Data
tHZR or tLZR
SYNC Symbol or DIN0-9
1.5V
0.8V
Enable
Chx_txclk
Pad_Chx_p/n
Chx_lock
Chx-rxd
[N-1,0]
Chx_rxclk
OE
VCC
DSR2
t
SYNC patterns
Data
ZLR
t
t
ZHR or
SYNC Symbol or DIN0-9
t HZR or tLZR
0.0V
0.8V
1.2V
1.0V