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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
6
Electrical Specifications - LVDS SERDES
LVDS SERDES Transceiver Capability (Speed)
General Test Conditions
All tests are done for the 484-pin BGA package (1.00 mm pitch). The tests are set up so
that an LVDS SERDES channel of a QL82SD transmits, and the other LVDS SERDES
channel of the same device (or another QL82SD device) receives. All results are given as
worst cases over commercial temperature, VCC, and process, with PLLVCC = 2.5 V unless
otherwise specified.
If the QL82SD device is used only for transmit or receive, but not both simultaneously, the
performance can be significantly better, and, in many cases, exceeds 1 Gb/s per channel.
NOTE: All data are in Mb/s. Low/High frequencey refers to internal SERDES PLL lock
range (see Table 29 on page 31 for more information).
PT280
18.5
17.0
15.5
14.0
7.0
2.24
PS484
28.0
26.0
25.0
23.0
9.0
2.42
PB516
20.0
19.0
17.5
16.0
7.0
2.51
Table 5: Operating Ranges
Symbol
Parameter
Industrial
Commercial
Unit
Min
Max
Min
Max
Vcc
Supply Voltage
2.3
2.7
2.3
2.7
V
Vccio
I/O Input Tolerance Voltage
2.3
3.6
2.3
3.6
V
TA
Ambient Temperature
-40
85
0
70
°C
K
Delay Factor
-4 Speed Grade
0.43
2.16
0.47
2.11
n/a
-5 Speed Grade
0.43
1.80
0.46
1.76
n/a
-6 Speed Grade
0.43
1.26
0.46
1.23
n/a
-7 Speed Grade
0.43
1.14
0.46
1.11
n/a
Table 4: Thermal and Power Dissipation Characteristics
Package
0ja (*C/W vs. Airflow
0jc (*C/W)
Estimated Maximum
Power Dissipation (W)
0.0
0.5
1.0
2.0
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