www.quicklogic.com
© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
2
Programmable I/O
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Up to 252 Programmable I/O pins
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High performance Enhanced I/O (EIO): Less than 3 ns Tco
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Programmable Slew Rate Control
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Programmable I/O Standards
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LVTTL, LVCMOS, PCI, GTL+, SSTL2, and SSTL3, LVDS, LVPECL
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Four Independent I/O Banks
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Three Register Configuration: Input, Output, OE
Embedded Computational Unit (ECU) Blocks
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Integrated multiply, add, and accumulate function
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18 distributed MAC blocks
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8
× 8 multiply (sign & unsigned)
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16-bit carry add
Advanced Clock Network
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Nine Global Clock Networks consisting of:
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one dedicated
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eight programmable
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Eight I/O (high drive) networks: two I/Os per bank
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Ten Quad-Net Networks—five per quadrant
Figure 1: QL82SD Device Block Diagram
Table 1: QL82SD Device Table
Customer Part #
SERDES
Data
LVDS
Clocks
SRAM
Blocks
Logic
Cells
ECU
Blocks
Programmable I/O
QL82SD-PQ208
4
2
36
2016
18
75
QL82SD-PT280
8
2
36
2016
18
121
QL82SD-PS484
8
2
36
2016
18
209
QL82SD-PB516
8
2
36
2016
18
252
RAM Blocks
Embedded Computational Units (ECUs)
RAM Blocks
IO Block
IO Block
2016 Logic Cells
LVDS/SERDES IO Block
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