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© 2002 QuickLogic Corporation
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QL82SD Device Data Sheet Rev C
Preliminary
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IEEE Standard 1149.1a
The QuickSD device supports IEEE standard 1149.1a. The following public instructions are
supported: BYPASS, EXTEST, and SAMPLE/PRELOAD. Two additional modes RAMWT
and RAMRD can be used to load the RAM.
Figure 55: JTAG Block Diagram
JTAG BSDL Support
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BSDL-Boundary Scan Description Language
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Machine-readable data for test equipment to generate testing vectors and software
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BSDL files available for all device/ package combinations from QuickLogic
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Extensive industry support available and ATG (Automatic Test-vector Generation)
Security Fuses
There are two security links, one to disable reading from the array and the other to disable
JTAG.
8-bit Programming
The QuickSD device has 8-bit programming capability. The addition of four extra
programming supplies is used in the reduction of programming time.
TCK
TMS
TRSTB
Logic Cell
Array
I/O Registers
User Defined Data Register
Bypass
Register
Boundary-Scan Register
(Data Register)
Mux
Instruction Register
Mux
Tap Controller
State Machine
(16 States)
Instruction Decode
&
Control Logic
RDI
TDO
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