ST7LUS5 datasheet(109/124 Pages) STMICROELECTRONICS

109 / 124 page

ST7LUS5, ST7LU05, ST7LU09

Electrical characteristics

109/124

Figure 56.

RESET pin protection when LVD is enabled(1)(2)(3)(4)

- The reset network protects the device against parasitic resets.

- The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

- Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin

can go below the VIL max. level specified in Table 81 on page 108. Otherwise the reset will not be taken

into account internally.

- Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user

must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for

IINJ(RESET) in Table 62 on page 92.

When the LVD is enabled, it is recommended not to connect a pull-up resistor or capacitor. A 10nF pull-

down capacitor is required to filter noise on the reset line.

In case a capacitive power supply is used, it is recommended to connect a 1M

Ω pull-down resistor to the

RESET pin to discharge any residual voltage induced by the capacitive effect of the power supply (this will

add 5µA to the power consumption of the MCU).

Tips when using the LVD:

A. Check that all recommendations related to ICCCLK and reset circuit have been applied (see caution in

Table 2 on page 13 and notes above)

B. Check that the power supply is properly decoupled (100nF + 10µF close to the MCU). Refer to AN1709

and AN2017. If this cannot be done, it is recommended to put a 100nF + 1M

Ω pull-down on the RESET

pin.

C. The capacitors connected on the RESET pin and also the power supply are key to avoid any start-up

marginality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace

10nF pull-down on the RESET pin with a 5µF to 20µF capacitor.”

Figure 57.

RESET pin protection when LVD is disabled(1)

The reset network protects the device against parasitic resets.

The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad.

Otherwise the device can be damaged when the ST7 generates an internal reset (LVD or watchdog).

Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin

can go below the VIL max. level specified in Table 81 on page 108. Otherwise the reset will not be taken

into account internally.

Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user

must ensure that the current sunk on the RESET pin is less than the absolute maximum value specified for

IINJ(RESET) in Table 62 on page 92.

Please refer to Illegal opcode reset on page 87 for more details on illegal opcode reset conditions

ST7XXX

PULSE

GENERATOR

Filter

RON

VDD

INTERNAL

RESET

EXTERNAL

Required

Ω

Optional

(note 3)

WATCHDOG

LVD RESET

ILLEGAL OPCODE(5)

0.1µF

0.01µF

EXTERNAL

RESET

CIRCUIT

USER

Required

ST7XXX

PULSE

GENERATOR

Filter

RON

VDD

INTERNAL

RESET

WATCHDOG

ILLEGAL OPCODE(2)

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