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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST7LUS5 датащи(PDF) 68 Page - STMicroelectronics |
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ST7LUS5 датащи(HTML) 68 Page - STMicroelectronics |
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68 / 124 page  On-chip peripherals ST7LUS5, ST7LU05, ST7LU09 68/124 10.2.2 Main features ● 12-bit up counter with 12-bit autoreload register (ATR) ● Maskable overflow interrupt ● PWM signal generator ● Frequency range 2 kHz to 4 MHz (@ 8 MHz fCPU) – Programmable duty-cycle – Polarity control – Maskable Compare interrupt ● Output Compare Function Figure 31. Block diagram 10.2.3 Functional description PWM mode This mode allows a Pulse Width Modulated signals to be generated on the PWM0 output pin with minimum core processing overhead. The PWM0 output signal can be enabled or disabled using the OE0 bit in the PWMCR register. When this bit is set the PWM I/O pin is configured as output push-pull alternate function. Note: CMPF0 is available in PWM mode (see PWM0CSR register description on page 74). ATCSR CMPIE OVFIE OVF CK0 CK1 0 0 0 12-BIT AUTORELOAD VALUE 12-BIT UPCOUNTER CMPF0 bit CMPF0 CMP INTERRUPT REQUEST OVF INTERRUPT REQUEST fCPU ATR POL- ARITY OP0 bit PWM0 COMP- PARE fCOUNTER fPWM OE0 bit CNTR (1ms timebase fLTIMER DCR0H DCR0L Update on OVF Event Preload Preload @ 8 MHz) 70 on OVF Event 0 1 12-BIT DUTY CYCLE VALUE (shadow) OE0 bit IF OE0=1 |
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